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visit our website: www.e2v.com for the latest version of the datasheet e2v semiconductors sas 2009 pc8610 integrated host processor hardware specifications datasheet - preliminary specification features ? e600 power architecture ? processor core ? pd maximum 16w at 1.33 ghz (v dd = 1.025v) ; 13w at 1.066 ghz (v dd = 1.00v) ? selectable mpx bus up to 533 mhz ? integrated l1: 32 kb instruction and 32 kb data cache (with parity protection) ? integrated l2: 256 kb backsi de cache with optional ecc ? lcd controller: maximum display resolution sxga 1280 1024 with 60 hz refresh ? pci express interface: one 1x, 2x, 4x or 8x and one 1x, 2x or 4x serial (2.5 gbaud/lane) ? audio interface: two synchronous serial interface (ssi) controllers for i2s or ac97 audio inputs/outputs ? memory controller: ddr/ddr2 sdram with ecc (333, 400 and 533 mhz data rates) ? dma controller: two four-channel controllers ? other interfaces: two fast infra-red interfaces (firi) ? f int max = 1333 mhz ? f bus max = 533 mhz overview the pc8610 features a high-performance, superscalar e600 core operating between 667 mhz and 1333 mhz. its smaller 256 kb backside l2 cache saves power and cost for target applications that typically don?t need the full 1 mb cache avail- able in other e600-based devices. the core also includes the altivec ? 128-bit vector processing engine which eembc benchmarks show to give a 3 to 10 times performance increase. screening ? full military temperature range (t c = ?55 c, t j = +125 c) ? industrial temperature range (t c = ?40 c, t j = +110 c) 0926d?hirel?12/09
2 0926d?hirel?12/09 pc8610 [preliminary] e2v semiconductors sas 2009 1. block diagram figure 1-1 shows the major functional units within the pc8610. figure 1-1. pc8610 block diagram ddr/ddr2 sdram irqs mpx bus rom, nand flash, nor flash, gpio serial i 2 c irda spi peripherals lcd timer control pci express x1,x2,x4,x8 external control pci express x1,x2,x4 32-bit pci external control 32-bit pci interface four-channel dma controller 1 four-channel dma controller 2 pci express (x8) interface 2 pci express (x4) interface 1 ocean switch fabric 1 programmable interrupt controller (pic) ddr/ddr2 sdram controller 2 x i 2 c controller 2 x dual universal asynchronous receiver/transmitter (duart) 2 x fast/serial infra-red interface (firi/siri) serial peripheral interface display interface unit 2 x global timer module local bus controller (elbc) 256-kbyte l2 cache e600 core block 32-kbyte l1 instruction cache 32-kbyte l1 data cache e600 core w/ altivec mpx coherency module (mcm) i 2 s/ac97 audio synchronous serial interface (ssi) ocean switch fabric 2
3 0926d?hirel?12/09 e2v semiconductors sas 2009 pc8610 [preliminary] 1.1 key features ? high-performance, 32-bit power architecture e600 core ? eleven execution units and three register files ? two separate 32-kbyte instruction and data level 1 (l1) caches ? integrated 256-kbyte, eight-way set-associative unified instruction and data level 2 (l2) cache with ecc ? 36-bit real addressing ? multiprocessing support features ? power and thermal management ? mpx coherency module (mcm) ? address translation and mapping units (atmus) ? ddr/ddr2 memory controller ? 64- or 32-bit data path (72-bit with ecc) ? up to 533-mhz ddr2 data rate and up to 400 mhz ddr data rate ? up to 16 gbytes memory ? enhanced local bus controller (elbc) ? operating at up to 133 mhz ? eight chip selects ? display interface unit ? maximum display resolution: 1280 1024 ? maximum display refresh rate: 60 hz ? display color depth: up to 24 bpp ? display interface: parallel ttl ? openpic-compliant programmable interrupt controller (pic) ? supports 16 programmable interrupt and processor task priority levels ? supports 12 discrete external interrupts and 48 internal interrupts ? eight global high resolution timers/counters that can generate interrupts ? support for pci express message-shared interrupts (msis) ?dual i 2 c controllers ? master or slave i 2 c mode support ? boot sequencer ? optionally loads configuration data from serial rom at reset via i 2 c interface ? can be used to initialize configuration registers and/or memory ? supports extended i 2 c addressing mode ?duart ? fast infrared interface ? serial peripheral interface ? master or slave support ? dual integrated four-channel dma controllers ? all channels accessible by both local and remote masters
4 0926d?hirel?12/09 pc8610 [preliminary] e2v semiconductors sas 2009 ? supports transfers to or from any local memory or i/o port ? ability to start and flow control each dm a channel from extern al 3-pin interface ? watchdog timer ? dual global timer modules ? 32-bit pci interface, 33 or 66 mhz bus frequency ? dual pci express controllers ? pci express 1.0a compatible ? pci express controller 1 supports x1, x2, and x4 link widths; pci express controller 2 supports x1, x2, x4, and x8 link widths ? 2.5 gbaud, 2.0 gbps lane ? device performance monitor ? supports eight 32-bit counters that count the occurrence of selected events ? ability to count up to 512 counter-spe cific events ? supports 64 reference events that can be counted on any of the 8 counters ? supports duration and quantity threshold counting ? burstiness feature that permits counting of burst events with a programmable time between bursts ? triggering and ch aining capability ? ability to generate an interrupt on overflow ? ieee 1149.1-compliant, jtag boundary scan ? available as 783-pin, flip-chip, plastic ball grid array (fc-pbga) 2. pin assignments and reset states 2.1 pin assignments table 2-1 provides the pin assignments for the signals. table 2-1. signal reference by functional block name (1) package pin number pin type power supply notes clocking signals (4) sysclk d28 i ov dd rtc a25 i ov dd ddr memory interface signals (2) ma[15:0] ah28, ah25, ah6, ah24, ah22, ag13, ag22, ag19, ah21, ah19, ah18, ag16, ah16, ag15, ah15, ah14 ogv dd mba[2:0] ag25, ah13, ah12 o gv dd mcs [0:3] ah10, ag7, ah9, ag4 o gv dd
5 0926d?hirel?12/09 e2v semiconductors sas 2009 pc8610 [preliminary] mdq[0:63] w26, y26, ab24, ac28, w27, y28, ab27, ab26 ad27, ae27, ad25, af25, ac26, ad28, ac25, ad24, ag24, af23, ae21, ag21, ae24, ae23, af22, ad21, ah20, ac19, ag18, af17, ae20, af20, ae18, ac17, ac13, ad12, ag9, ae9, ad13, ae12, ad10, ac10, af8, ae8, ad6, ah5, ad9, ah8, ag6, ae6, af4, ad4, ac3, ac1, af5, ae5, ad2, ac4, ab1, ab2, y1, y6, ab6, aa6, y3, y4 i/o gv dd mecc[0:7] ad16, af16, ac15, af15, ah17, ae17, aa15, ab15 i/o gv dd mdm[0:8] y25, ae26, ah23, ad19, af11, af7, ae3, ab4, ac16 o gv dd mdqs[0:8] aa25, af26, ad22, ad18, af10, ac7, ad3, aa5, y15 i/o gv dd mdqs [0:8] aa27, af28, ac22, af19, ae11, ad7, ae2, ab5, ab16 i/o gv dd mcas ag10 o gv dd mwe ah11 o gv dd mras ag12 o gv dd mck[0:5] af14, ag28, ah3, ad15, ah27, ag2 o gv dd mck [0:5] af13, ag27, ah2, ad14, ah26, ag1 o gv dd mcke[0:3] ab28, aa28, ae28, w28 o gv dd mdic[0:1] ad1, ae1 i/o gv dd modt[0:3] ah7, ah4, ag3, af1 o gv dd enhanced local bus signals (4) lad[0:31] aa21, aa22, aa23, y21, y22, y23, y24, w23, w24, w25, v28, v27, v25, v23, v21, w22, u28, u26, u24, u22, u23, u20, u21, w20, v20, t24, t25, t27, t26, t21, t22, t23 i/o bv dd ldp[0:3]/la[6:9] n28, m28, l28, p25 i/o bv dd la10/ssi1_txd p19 o bv dd la11/ssi1_tfs m27 o bv dd la12/ssi1_tck u18 o bv dd la13/ssi1_rck p28 o bv dd la14/ssi1_rfs r18 o bv dd la15/ssi1_rxd r19 o bv dd la16/ssi2_txd r20 o bv dd la17/ssi2_tfs m18 o bv dd la18/ssi2_tck n18 o bv dd la19/ssi2_rck n27 o bv dd la20/ssi2_rfs p20 o bv dd la21/ssi2_rxd p21 o bv dd la[22:31] m19, m21, m22, m23, n23, n24, m26, n20, n21, n22 o bv dd lcs [0:4] r24, r22, p23, p24, p27 o bv dd lcs5 /dma2_dreq0 r23 o bv dd lcs6 /dma2_dack0 n26 o bv dd table 2-1. signal reference by functional block (continued) name (1) package pin number pin type power supply notes
6 0926d?hirel?12/09 pc8610 [preliminary] e2v semiconductors sas 2009 lcs7 /dma2_ddone0 r26 o bv dd lwe0 /lfwe /lbs0 t19 o bv dd lwe1 /lbs1 t20 o bv dd lwe2 /lbs2 w19 o bv dd lwe3 /lbs3 t18 o bv dd lbctl t28 o bv dd lale r28 o bv dd lgpl0/lfcle l19 o bv dd lgpl1/lfale l20 o bv dd lgpl2/loe /lfre l21 o bv dd lgpl3/lfwp l22 o bv dd lgta /lfrb / lgpl4/lupwait/lpbse l23 i/o bv dd lgpl5 l24 o bv dd lclk[0:2] r25, m25, l26 o bv dd diu/lcd signals (4) diu_ld[23:16] r3, r10, t10, n7, n4, p6, p5, p4 o ov dd (5) gpio1[15:8] diu_ld[15:0] t3, r9, t9, r8, r7, r6, r4, t7, u5, t6, t5, w4, w5, w6, v4, v6 oov dd (5) gpio1[31:16] diu_vsync v7 o ov dd diu_hsync u7 o ov dd diu_de u4 o ov dd diu_clk_out n6 o ov dd programmable interrupt controller (pic) signals (4) irq[0:5] l25, j23, k26, e23, k28, k22 i ov dd irq6/dma1_dreq0 g27 i ov dd irq7/dma1_dack0 j25 i ov dd irq8/dma1_ddone0 j27 i ov dd irq9/dma1_dreq3 h26 i ov dd irq10/dma1_dack3 j26 i ov dd irq11/dma1_ddone3 k27 i ov dd irq_out k23 o ov dd mcp a24 i ov dd smi b24 i ov dd i 2 c signals iic1_sda d24 i/o ov dd gpio2[10] iic1_scl e24 i/o ov dd gpio2[9] table 2-1. signal reference by functional block (continued) name (1) package pin number pin type power supply notes
7 0926d?hirel?12/09 e2v semiconductors sas 2009 pc8610 [preliminary] iic2_sda/spisel e27 i/o ov dd gpio2[12] iic2_scl/spiclk e28 i/o ov dd gpio2[11] duart signals (4) uart_sin0/spimosi k24 i ov dd gpio2[5] uart_sout0/spimiso h25 o ov dd uart_cts0 g24 i ov dd gpio2[6] uart_rts0 g26 o ov dd uart_sin1/ir2_rxd f25 i ov dd gpio2[7] uart_sout1/ir2_txd h24 o ov dd uart_cts 1c23 i ov dd gpio2[8] uart_rts 1d23 o ov dd irda signals (4) ir1_txd f27 o ov dd gpio2[13] ir1_rxd e26 i ov dd gpio2[14] ir_clkin f28 i ov dd ir2_txd/uart_sout1 h24 o ov dd ir2_rxd/uart_sin1 f25 i ov dd gpio2[7] spi signals spimosi/uart_sin0 k24 i/o ov dd gpio2[5] spimiso/uart_sout0 h25 i/o ov dd spisel /iic2_sda e27 i ov dd gpio2[12] spiclk/iic2_scl e28 i ov dd gpio2[11] ssi signals (3)(6) ssi1_rxd/la15 r19 i bv dd ssi1_txd/la10 p19 o bv dd ssi1_rfs/la14 r18 i/o bv dd ssi1_tfs/la11 m27 i/o bv dd ssi1_rck/la13 p28 i/o bv dd ssi1_tck/la12 u18 i/o bv dd ssi2_rxd/la21 p21 i bv dd ssi2_txd/la16 r20 o bv dd ssi2_rfs/la20 p20 i/o bv dd ssi2_tfs/la17 m18 i/o bv dd ssi2_rck/la19 n27 i/o bv dd ssi2_tck/la18 n18 i/o bv dd dma signals (4) dma1_dreq0 /irq6 g27 i ov dd gpio2[24] table 2-1. signal reference by functional block (continued) name (1) package pin number pin type power supply notes
8 0926d?hirel?12/09 pc8610 [preliminary] e2v semiconductors sas 2009 dma1_dreq3 /irq9 h26 i ov dd gpio2[26] dma1_dack0 /irq7 j25 o ov dd gpio2[25] dma1_dack3 /irq10 j26 o ov dd gpio2[27] dma1_ddone0 /irq8 j27 o ov dd dma1_ddone3 /irq11 k27 o ov dd gpio2[28] dma2_dreq0 /lcs5 r23 i ov dd dma2_dreq3 h27 i ov dd gpio2[29] dma2_dack0 /lcs6 n26 o ov dd dma2_dack3 h28 o ov dd gpio2[30] dma2_ddone0 /lcs7 r26 o ov dd dma2_ddone3 j28 o ov dd gpio2[31] general-purpose timer signals (4) gtm1_tin1 u3 i ov dd gpio2[15] gtm1_tin3 w2 i ov dd gpio2[21] gtm1_tgate 1v2 i ov dd gpio2[16] gtm1_tgate 3u1 i ov dd gpio2[22] gtm1_tout 1w3 o ov dd gpio2[17] gtm1_tout 3u2 o ov dd gpio2[23] gtm2_tin1 v1 i ov dd gpio2[18] gtm2_tgate 1w1 i ov dd gpio2[19] gtm2_tout 1v3 o ov dd gpio2[20] pci signals (4) pci_ad[31:0] m1, m2, m3, m4, m5,m7, l1, l6, j1, k2, k3, k4, k5, k6, k7, h1, h7, g1, g2, g3, g4, g5, g6, f1, f4, f6, f7, f8, d2, d3, e1, e2 i/o ov dd pci_c/be [3:0] l2, j2, h6, f2 i/o ov dd pci_par h5 i/o ov dd pci_frame j3 i/o ov dd pci_trdy j6 i/o ov dd pci_irdy j5 i/o ov dd pci_stop e4 i/o ov dd pci_devsel j7 i/o ov dd pci_idsel l5 i ov dd pci_perr h2 i/o ov dd pci_serr h3 i/o ov dd pci_req0 n3 i/o ov dd pci_req1 n1 i/o ov dd gpio1[0] pci_req2 p3 i/o ov dd gpio1[2] table 2-1. signal reference by functional block (continued) name (1) package pin number pin type power supply notes
9 0926d?hirel?12/09 e2v semiconductors sas 2009 pc8610 [preliminary] pci_req3 p1 i/o ov dd gpio1[4] pci_req4 p2 i/o ov dd gpio1[6] pci_gnt0 n2 i/o ov dd pci_gnt1 t1 i/o ov dd gpio1[1] pci_gnt2 t2 i/o ov dd gpio1[3] pci_gnt3 r1 i/o ov dd gpio1[5] pci_gnt4 r2 i/o ov dd gpio1[7] pci_clk c1 i ov dd serdes 1 signals sd1_tx[3:0] j13, g12, f10, h9 o x1v dd sd1_tx [3:0] h13, f12, g10, j9 o x1v dd sd1_rx[3:0] b9, d8, d5, b4 i s1v dd sd1_rx [3:0] a9, c8, c5, a4 i s1v dd sd1_ref_clk a7 i s1v dd sd1_ref_clk b7 i s1v dd sd1_pll_tpd c7 o x1v dd (9)(10) sd1_pll_tpa b6 analog s1v dd (9)(11) sd1_imp_cal_tx e11 analog x1v dd (7) sd1_imp_cal_rx b3 analog s1v dd (8) serdes 2 signals sd2_tx[7:0] f22, j21, f20, h19, j17, g16, h15, g14 o x2v dd sd2_tx [7:0] g22, h21, g20, j19, h17, f16, j15, f14 o x2v dd sd2_rx[7:0] b22, d21, b20, d19, c15, b14, c13, a12 i s2v dd sd2_rx [7:0] a22, c21, a20, c19, d15, a14, d13, b12 i s2v dd sd2_ref_clk a18 i s2v dd sd2_ref_clk b18 i s2v dd sd2_pll_tpd d17 o x2v dd (9)(10) sd2_pll_tpa c17 analog s2v dd (9)(11) sd2_imp_cal_tx e21 analog x2v dd (7) sd2_imp_cal_rx b11 i s2v dd (8) system control signals (4) hreset b23 i ov dd hreset_req j22 o ov dd sreset a26 i ov dd ckstp_in c27 i ov dd ckstp_out f24 o ov dd power management signals (4) table 2-1. signal reference by functional block (continued) name (1) package pin number pin type power supply notes
10 0926d?hirel?12/09 pc8610 [preliminary] e2v semiconductors sas 2009 asleep b26 o ov dd debug signals (4) trig_in k20 i ov dd trig_out/ready/quie sce c28 o ov dd msrcid[0:4] y20, ab23, ab20, ab21, ac23 o bv dd (14) mdval ac20 o bv dd clk_out g28 o ov dd test signals (4) lssd_mode g23 i ov dd test_mode0 k12 i ov dd test_mode1 k10 i ov dd jtag signals (4) tck d26 i ov dd tdi b25 i ov dd tdo d27 o ov dd tms c25 i ov dd trst a28 i ov dd additional analog signals temp_anode c11 thermal - temp_cathode c10 thermal - special connection requirement pins no connects b1, b10, c2, c3, e22, f18, g11, g18, h8, h11, h14, j11, aa1, aa2, aa3, aa4 ?? (15) power and ground signals mv ref ae14 ddr2 reference voltage gv dd /2 ov dd c24, c26, d1, e25, f3, g7, g25, h4, j24, k1, l4, l7, n5, p10, p7, t4, t8, v5, v8 lcd, general purpose timer, pci, mpic, i2c, duart, irda, spi, dma, system control, clocking, debug, test, jtag, & power management i/o supply ov dd gv dd y2, y16, aa7, aa24, aa26, ab14, ab17, ac2, ac5, ac6, ac9, ac12, ac18, ac21, ac24, ac27, ae4, ae7, ae10, ae13, ae16, ae19, ae22, ae25, af2, ag5, ag8, ag11, ag14, ag17, ag20, ag23, ag26, ah1 ddr sdram i/o supply gv dd table 2-1. signal reference by functional block (continued) name (1) package pin number pin type power supply notes
11 0926d?hirel?12/09 e2v semiconductors sas 2009 pc8610 [preliminary] bv dd l27, m20, m24, p18, p22, p26, u19, u27, v24, w21, aa20 elbc & ssi i/o voltage bv dd s1v dd a3, a10, b5, b8, d4, d7 receiver and serdes core power supply for port 1 s1v dd s2v dd a11, a15, a19, a23, b13, b17, b21, c14, c18, d12, d16, d20 receiver and serdes core power supply for port 2 s2v dd x1v dd f11, g9, h12, j10, k13 transmitter power supply for serdes port 1 x1v dd x2v dd f13, f17, f21, g15, g19, h18, h22, j16, j20 transmitter power supply for serdes port 2 x2v dd l1v dd k14 digital logic power supply for serdes port 1 l1v dd l2v dd k16, k18 digital logic power supply for serdes port 2 l2v dd v dd _core l8, l10, m9, m11, m13, m15, n8, n10, n12, n14, n16, p9, p11, p13, p15, r12, r14, r16, t11, t13, t15, u10, u12, u14, u16, v9, v11, v13, v15, w8, w10, w12, w14, w16, y9, y11, y13, y7, aa8, aa10, aa12, ab9, ab11, ac8 core voltage supply v dd _core v dd _plat l12, l14, l16, l18, m17, p17, t17, v17, v19, w18, y17, y19, aa18 platform supply voltage v dd _plat av dd _core a27 core pll supply av dd _core av dd _plat b28 platform pll supply av dd _plat av dd _pci a2 av dd _pci sd1av dd a6 sd1av dd sd2av dd a16 sd2av dd sensev dd ac11 v dd _core sensing pin sensev ss ab12 core gnd sensing pin gnd b2, b27, d25, e3, f26, f5, g8, h23, j4, k25, l11, l13, l15, l17, l3, l9, m10, m12, m14, m16, m6, m8, n11, n13, n15, n17, n19, n25, n9, p12, p14, p16, p8, r11, r13, r15, r17, r21, r27, r5, t12, t14, t16, u11, u13, u15, u17, u25, u6, u8, u9, v10, v12, v14, v16, v18, v22, v26, w11, w13, w15, w17, w7, w9, y10, y12, y14, y18, y27, y5, y8, aa11aa13, aa14, aa16, aa17, aa19, aa9, ab10, ab13, ab18, ab19, ab22, ab25, ab3, ab7, ab8, ac14, ad11, ad17, ad20, ad23, ad26, ad5, ad8, ae15, af12, af18, af21, af24, af27, af3, af6, af9 gnd table 2-1. signal reference by functional block (continued) name (1) package pin number pin type power supply notes
12 0926d?hirel?12/09 pc8610 [preliminary] e2v semiconductors sas 2009 sd1agnd c6 serdes port 1 ground pin for sd1av dd sd2agnd b16 serdes port 2 ground pin for sd2av dd sgnd a5, a8, a13, a17, a21, b15, b19, c4, c9, c12, c16, c20, c22, d6, d9, d10, d11, d14, d18, d22, e5, e6, e7, e8, e9, e10, e13, e14, e15, e16, e17, e18, e19, e20 ground pins for sv dd xgnd e12, f9, f15, f19, f23, g13, g17, g21, h10, h16, h20, j8, j12, j14, j18, k8, k9, k11, k15, k17, k19, k21 ground pins for xv dd reset configuration signals (15) lad[0:31] cfg_gpinout[0:31] aa21, aa22, aa23, y21, y22, y23, y24, w23, w24, w25, v28, v27, v25, v23, v21, w22, u28, u26, u24, u22, u23, u20, u21, w20, v20, t24, t25, t27, t26, t21, t22, t23 ?bv dd la10/ssi1_txd cfg_ssi_la_sel p19 ? bv dd la[25:26] cfg_elbc_clkdiv[0:1] m23, n23 ? bv dd la27 cfg_cpu_boot n24 ? bv dd diu_ld[10], la[28:31] cfg_sys_pll[0:4] r6, m26, n20, n21, n22 ? bv dd lwe0 /lfwe /lbs0 cfg_pci_speed t19 ? bv dd lwe /lbs [1:3] cfg_host_agt[0:2] t20, w19, t18 ? bv dd lbctl, lale, lgpl2/loe /lfre , diu_ld4 cfg_core_pll[0:3] t28, r28, l21, w4 ? bv dd lgpl0/lfcle cfg_net2_div l19 ? bv dd (12) lgpl1/lfale cfg_pci_clk l20 ? bv dd lgpl3/lfwp , lgpl5 cfg_boot_seq[0:1] l22, l24 ? bv dd diu_ld[0] cfg_elbc_ecc v6 ? ov dd gpio1[16] diu_ld[7:9] cfg_io_ports[0:2] u5, t7, r4 ? ov dd gpio1[23:25] diu_ld[11:12] cfg_dram_type[0:1] r7, r8 ? ov dd gpio1[27:28] diu_de, diu_ld[13:15] cfg_rom_loc[0:3] u4, t9, r9, t3 ? ov dd gpio1[29:31] diu_vsync cfg_pci_impd v7 ? ov dd table 2-1. signal reference by functional block (continued) name (1) package pin number pin type power supply notes
13 0926d?hirel?12/09 e2v semiconductors sas 2009 pc8610 [preliminary] notes: 1. multi-pin signals such as ldp[0:3] have their physical package pin numbers listed in order corresponding to the signal names. 2. stub series terminated logic type pins. 3. all ssi signals are multiplexed with elbc signals. 4. low voltage transistor-transistor logic (lvttl) type pins. 5. diu_ld[23:16] = red[7:0] diu_ld[15:8] = green[7:0] diu_ld[7:0] = blue[7:0] 6. the pins for the ssi interface on the device are multiplexed with certain elbc signals, which have the ability to operate at a different voltage than the other standard i/o signals. if the device is configured such that the elbc uses a different voltage than standard i/o and an ssi port on the device is used, then level shifters are required on the ssi signals to ensure they correctly interface to other devices on the board at the proper voltage. 7. this pin should be pulled to ground with a 100 resitor. 8. this pin should be pulled to ground with a 200 resitor. 9. these pins should be left floating. 10. this is a serdes pll/dll digital test signal and is only for factory use. 11. this is a serdes pll/dll analog test signal and is only for factory use. 12. this pin should be pulled down if the platform frequency is 400 mhz or below. 13. this pin should be pulled down if the core frequency is 800 mhz or below. 14. msrcid1 should be pulled high during reset.15. the pins in this section are reset configuration pins. each pin has a weak internal pull-up p-fet which is enabled only when the processor is in the reset state. this pull-up is designed such that it can be overpowered by an external 4.7-k pull-down resistor. however, if the signal is intended to be high after reset, and if there is any device on the net which might pull down the value of the net at reset, then a pullup or active driver is needed. 15. these pins should be left floating. diu_hsync cfg_pci_arb u7 ? ov dd uart_rts0 cfg_wdt_en g26 ? ov dd asleep cfg_core_speed b26 ? ov dd (13) msrcid0 cfg_mem_debug y20 ? bv dd mdval cfg_boot_vector ac20 ? bv dd table 2-1. signal reference by functional block (continued) name (1) package pin number pin type power supply notes
14 0926d?hirel?12/09 pc8610 [preliminary] e2v semiconductors sas 2009 3. electrical characteristics this section provides the ac and dc electrical s pecifications for the pc8610. the pc8610 is currently targeted to these specifications. 3.1 overall dc electr ical characteristics this section covers the ratings, conditions, and other characteristics. 3.1.1 absolute maximum ratings table 3-1 provides the absolute maximum ratings. notes: 1. functional and tested operating conditions are given in table 3-2 on page 15 . absolute maximum ratings are stress ratings only, and functional operation at the maximums is not guarantee d. stresses beyond those listed may affect device reliability or cause permanent damage to the device. 2. during run time (m, b, o)v in and mv ref may overshoot/undershoot to a voltage and for a maximum duration as shown in table 3-1 on page 14 table 3-1. absolute maximum ratings (1) characteristic symbol recommended value unit notes core supply voltages v dd _core ?0.3 to 1.21v v core pll supply av dd _core ?0.3 to 1.21v v serdes receiver and core power supply (ports 1 and 2) s1v dd s2v dd ?0.3 to 1.21v v serdes transmitter power supply (ports 1 and 2) x1v dd x2v dd ?0.3 to 1.21v v serdes digital logic power supply (ports 1 and 2) l1v dd l2v dd ?0.3 to 1.21v v serdes pll supply voltage (port 1 and port 2) sd1av dd sd2av dd ?0.3 to 1.21v v platform supply voltage v dd _plat ?0.3 to 1.21v v pci and platform pll supply voltage av dd _pci av dd _plat ?0.3 to 1.21v v ddr/ddr2 sdram i/o supply voltages gv dd ?0.3 to 2.75v v local bus and ssi i/o voltage bv dd ?0.3 to 3.63v v lcd, pci, general purpose timer, mpic, irda, duart, dma, interrupts, system control & clocking, debug, test, jtag, power management, i 2 c, spi and miscellaneous i/o voltage ov dd ?0.3 to 3.63v v input voltage ddr/ddr2 sdram signals mv in (gnd ?0.3) to (gv dd +0.3) v (2) ddr/ddr2 sdram reference mv ref (gnd ?0.3) to (gv dd /2 + 0.3) v (2) local bus i/o voltage bv in (gnd ?0.3) to (bv dd +0.3) v (2) lcd, pci, general purpose, mpic, irda, duart, dma, interrupts, system control & clocking, debug, test, jtag, power management, i 2 c, spi and miscellaneous i/o voltage ov in (gnd ?0.3) to (0v dd +0.3) v (2) storage temperature range t stg -55 to 150 c
15 0926d?hirel?12/09 e2v semiconductors sas 2009 pc8610 [preliminary] 3.1.2 recommended operating conditions table 3-2 provides the recommended operating conditions for the pc8610. note that the values in table 3-2 are the recommended and tested operating conditions. proper device operation outside of these conditions is not guaranteed. for details on order in formation and specific operating conditions for parts, see section 6. ?ordering information? on page 91 . notes: 1. applies to devices marked with a core frequency of 1333 mhz. refer to table part numbering nomenclature to determine if the device has been marked for a core frequency of 1333 mhz. table 3-2. recommended operating conditions characteristic symbol recommended value unit notes core supply voltages v dd _core 1.025 50 mv v (1) 1.00 50 mv (2) core pll supply av dd _core 1.025 50 mv v (1)(3) 1.00 50 mv (2)(3) serdes receiver and core power supply (ports 1 and 2) s1v dd s2v dd 1.025 50 mv v (1)(4) 1.00 50 mv (2) serdes transmitter power supply (ports 1 and 2) x1v dd x2v dd 1.025 50 mv v (1) 1.00 50 mv (2) serdes digital logic power supply (ports 1 and 2) l1v dd l2v dd 1.025 50 mv v (1) 1.00 50 mv (2) serdes pll supply voltage (port 1 and port 2) sd1av dd sd2av dd 1.025 50 mv v (1)(3) 1.00 50 mv (2)(3) platform supply voltage v dd _plat 1.025 50 mv v (1) 1.00 50 mv (2) pci and platform pll supply voltage av dd _pci av dd _plat 1.025 50 mv v (1)(3) 1.00 50 mv (2)(3) ddr and ddr2 sdram i/o supply voltages gv dd 2.5v 125 mv, 1.8v 90 mv v (5) local bus and ssi i/o voltage bv dd 3.3v 165 mv 2.5v 125 mv 1.8v 90 mv v lcd, pci, general timer, mpic, irda, duart, dma, interrupts, system control & clocking, debug, test, jtag, power management, i 2 c, spi and miscellaneous i/o voltage ov dd 3.3v 165 mv v (6) input voltage ddr and ddr2 sdram signals mv in (gnd - 0.3) to (gv dd + 0.3) v (7)(5) ddr and ddr2 sdram reference mv ref (gnd - 0.3) to (gv dd /2 + 0.3) v (7) local bus i/o voltage bv in (gnd - 0.3) to (bv dd + 0.3) (7) lcd, pci, general purpose timer, mpic, irda, duart, dma, interrupts, system control & clocking, debug, test, jtag, power management, i 2 c, spi and miscellaneous i/o voltage ov in (gnd - 0.3) to (ov dd + 0.3) v (7)(6) operating temperature t j t c t c = -55 c to t j = 125 c c
16 0926d?hirel?12/09 pc8610 [preliminary] e2v semiconductors sas 2009 2. applies to devices marked with a core frequency below 1333 mh z. refer to table part num bering nomenclature to deter- mine if the device has been marked for a core frequency below 1333 mhz. 3. avdd measurements are made at the input of the r/c filter described in section 4.2.1 ?pll power supply filtering? on page 73 and not at the processor pin. 4. pci express interface of the device is expected to receive signals from 0.175 to 1.2v. refer to section 3.18.4.3 ?differential receiver (rx) input specifications? on page 64 for more information. 5. caution: mv in must meet the overshoot/undershoot requirements for gv dd as shown in figure 3-1 on page 16 . 6. caution: ov in must meet the overshoot/ undershoot requirements for ov dd as shown in figure 3-1 on page 16 . 7. timing limitations for (m, b, o) v in and mv ref during regular run time is provided in figure 3-1 on page 16 . figure 3-1 shows the undershoot and overshoot voltages at the interfaces of the pc8610. figure 3-1. overshoot/undershoot voltage for m/b/ov in note: 1. t clk references clocks for various functional blocks as follows: for ddr, t clk references mck. for lbiu, t clk references lclk. for pci, t clk references pci_clk or sysclk. for i 2 c and jtag, t clk references sysclk. the pc8610 core voltage must always be provided at nominal v dd _core (see table 3-2 on page 15 for actual recommended core voltage). voltage to the external interface i/os are provided through separate sets of supply pins and must be provided at the voltages shown in table 3-2 on page 15 . the input volt- age threshold scales with respect to the associated i/o supply voltage. ov dd -based receivers are simple cmos i/o circuits and satisfy appropriate lvcmos type specif ications. the ddr sdram interface uses a single-ended differential receiver referenced to each externally supplied mv ref signal (nominally set to gv dd /2) as is appropriate for the (sstl-18 a nd sstl-2) electrical signaling standards. gnd gnd ? 0.3v gnd ? 0.7v g/o/b/x/sv dd + 20% g/o/b/x/sv dd + 5% v ih v il not to exceed 10% of t clk (1) g/o/b/x/sv dd
17 0926d?hirel?12/09 e2v semiconductors sas 2009 pc8610 [preliminary] 3.1.3 output driver characteristics table 3-3 provides information on the characteristics of the output driver strengths. the values are pre- liminary estimates. notes: 1. see the ddr control driver registers in the pc8610 reference manual for more information. 2. see the por impedance control register in the pc8610 refere nce manual for more information about local bus signals and their drive strength programmability. 3. see section 2.1 ?pin assignments? on page 4 for details on resistor requirements for the calibration of sd n _imp_cal_tx and sd n _imp_cal_rx transmit and receive signals. 4. stub series terminated logic (sstl-25) type pins. 5. stub series terminated logic (sstl-18) type pins. 6. the drive strength of the ddr interf ace in half strength mode is at t j = 125 c and at gv dd (min). 3.2 power sequencing the pc8610 requires its power rails to be applied in a specific sequence in order to ensure proper device operation. these requirements are as follows: the chronological order of power up is: 1. ov dd , bv dd 2. v dd _plat, av dd _plat, v dd _core, av dd _core, av dd _pci, snv dd , xnv dd , sd n av dd (this rail must reach 90% of its value before the rail for gv dd , and mv ref reaches 10% of its value) 3. gv dd , mv ref 4. sysclk the order of power down is as follows: 1. sysclk 2. gv dd , mv ref 3. v dd _plat, av dd _plat, v dd _core, av dd _core, av dd _pci, snv dd , xnv dd , sd n av dd 4. o dd , bv dd note: av dd type supplies must be delayed with respect to their source supplies by the rc time constant of the pll filter circuit described in section 4.2 ?power supply design and sequencing? on page 73 . table 3-3. output drive capability driver type programmable output impedance ( ) supply voltage notes ddr signals 18 36 (half strength mode) gv dd = 2.5v (1)(4)(6) ddr2 signal 18 36 (half strength mode) gv dd = 1.8v (1)(5)(6) local bus 25 35 bv dd = 3.3v bv dd = 2.5v (2) 45 (default) 45 (default) 125 bv dd = 3.3v bv dd = 2.5v bv dd = 1.8v pci, duart, dma, interrupts, system control & clocking, debug, test, jtag, power management and miscellaneous i/o voltage 45 ov dd = 3.3v i 2 c 150 ov dd = 3.3v pci express 100 xv dd = 1.0v (3)
18 0926d?hirel?12/09 pc8610 [preliminary] e2v semiconductors sas 2009 figure 3-2 illustrates the power up se quence as descr ibed above. figure 3-2. pc8610 power up sequencing notes: 1. dotted waveforms correspond to optional supply values for a specified power supply. see table 3-2 on page 15 . 2. the recommended maximum ramp up time for power supplies is 20 milliseconds. 3. refer to section 3.5 ?reset initia lization? on page 23 for additional information on pll relock and reset signal assertion timing requirements. 4. refer to table 4-7 on page 72 for additional information on reset configuration pin setup timing require- ments. in addition see figure 4-6 on page 79 regarding hreset and jtag connection details including trst . 5. e600 pll relock time is 100 microseconds maximum plus 255 mpx_clk cycles. 6. por configuration signals mu st be driven on reset. see section 3.5 ?reset init ialization? on page 23 for more information on setup and hold time of reset configuration signals. 7. the rail for v dd _plat, av dd _plat, v dd _core, av dd _core, av dd _pci, snv dd , xnv dd , and sd n av dd must reach 90% of its value before the rail for gv dd , and mv ref reaches 10% of its value. 8. sysclk must be driven only after the power for the various power supplies is stable. 9. the reset configuration signals for dram types must be valid before hreset is asserted. v dd _plat, av dd _plat ov dd time 2.5 v 3.3 v 0 dc power supply voltage reset configuration pins h reset (& trst) asserted for 100 s 4 v dd stable power supply ramp up 2 e600 5 av dd _pci, s n v dd , x n v dd v dd _core, av dd _core sd n av dd 1.8 v gv dd , = 1.8/2.5 v mv re f sysclk 8 (not drawn to scale) 7 pll 9 cycles setup and hold time 6 100 s platform pll relock time 3 0.95 v
19 0926d?hirel?12/09 e2v semiconductors sas 2009 pc8610 [preliminary] 3.3 power characteristics the estimated power dissipation for the pc8610 device is shown in table 3-4 . notes: 1. these values specify the power cons umption at nominal voltage and apply to all valid processor bus frequencies and conf ig- urations. the values do not include power dissipation for i/o supplies. 2. typical power is an average value measured at the nominal recommended core voltage (v dd _core) and 65 c junction tem- perature (see table 3-2 on page 15 )while running the dhrystone 2.1 benchmar k and achieving 2.3 dhrystone mips/mhz with the core at 100% efficiency. this parame ter is not 100% tested but periodically sampled. 3. thermal power is the average power measured at nominal core voltage (v dd _core) and maximum operating junction tem- perature (see table 3-2 on page 15 ) while running the dhrystone 2.1 benchmark and achieving 2.3 dhrystone mips/mhz on the core and a typical workload on platform interfaces. this parameter is not 100% tested but periodically sampled. 4. maximum power is the maximum power measured at nominal core voltage (v dd _core) and maximum operating junction temperature (see table 3-2 on page 15 ) while running a test which includes an entirely l1-cache-resident, contrived sequence of instructions which keep all the execution units maximally busy on the core. the estimated maximum power dissipation for indi vidual power supplies of the pc8610 is shown in table 3-5 on page 20 . table 3-4. pc8610 power dissipation power mode core/platform frequency (mhz) v dd _core, v dd _plat (volts) junction temperature ( c) power (watts) notes typical 1333/533 1.025 65 10.7 (1)(2) thermal 105 12.1 (1)(3) maximum 110 16 (1)(4) 125 18 (1)(4) typical 1066/533 1.00 65 8.4 (1)(2) thermal 105 9.5 (1)(3) maximum 110 13 (1)(4) 125 15 (1)(4) typical 800/400 1.00 65 5.8 (1)(2) thermal 105 7.2 (1)(3) maximum 110 9.5 (1)(4) 125 11 (1)(4)
20 0926d?hirel?12/09 pc8610 [preliminary] e2v semiconductors sas 2009 note: 1. this is a maximum power supply number which is provid ed for power supply and board design information. the numbers are based on 100% utilization for each component. the component s listed are not expected to have 100% usage simulta- neously for all components. actual numbers may vary based on ac tivity. note that the production parts should have a total maximum power value based on table 3-4 on page 19 . the ?est.? in the est. power colu mn is to emphasize that these num- bers are based on theoretical estimates. the device is tested to ensure that the sum of all four supplies does not exceed the power stated in table 3-4 . no specific supply should ever exce ed its individual amount estimated in table 3-5 on page 20 . 3.3.1 frequency derating to reduce power consumption, these devices s upport frequency derating if the reduced maximum pro- cessor core frequency and reduced maximum platform frequency requirements are observed. the reduced maximum processor core frequency, resu lting maximum platform frequency and power con- sumption are provided in table 3-6 . only those parameters in table 3-6 are affected; all other parameter specifications are unaffected. 3.4 input clocks table 3-7 provides the system clock (sysclk) dc specifications for the pc8610. note: 1. note that the symbol v in , in this case, represents the ov in symbol referenced in table 3-1 and table 3- 2 on page 15 . table 3-5. pc8610 individual supply maximum power dissipation (1) component description supply voltage (volts) est. power (watts) notes core voltage supply v dd _core = 1.025v at 1333 mhz 14.0 v dd _core = 1.00v at 1066 mhz 12.0 core pll voltage supply av dd _core = 1.025v at 1333 mhz 0.0125 av dd _core = 1.00v at 1066 mhz 0.0125 platform source supply v dd _plat = 1.025v at 1333 mhz 4.5 v dd _plat = 1.00v at 1066 mhz 4.3 platform pll voltage supply av dd _plat = 1.025v at 1333 mhz 0.0125 av dd _plat = 1.00v at 1066 mhz 0.0125 table 3-6. core frequency, platform frequency and power consumption derating maximum rated core frequency (device marking) maximum derated core/platform frequency (mhz) v dd _core, v dd _plat (v) typical power (watts) thermal power (watts) maximum power (watts) 1333j n/a 1066j 1000/400 1.00 8.0 9.4 t j = 110 c : 12.5 t j = 125 c : 14.5 800g 667/333 1.00 5.0 6.4 t j = 110 c : 8.5 t j = 125 c : 10.5 table 3-7. sysclk dc electrical characteristics (ov dd = 3.3 v 165 mv) parameter symbol min max unit high-level input voltage v ih 2ov dd + 0.3 v low-level input voltage v il ?0.3 0.8 v input current (v in (1) = 0 v or v in = v dd ) i in ?5a
21 0926d?hirel?12/09 e2v semiconductors sas 2009 pc8610 [preliminary] 3.4.1 system clock timing table 3-8 provides the system clock (sysclk) ac timing specificati ons for the pc8610. all specifications at recommended operating conditions (see table 3-2 on page 15 ) with ov dd = 3.3v 165 mv. notes: 1. caution: the platform to sysclk cloc k ratio and e600 core to plat form clock ratio settings mu st be chosen such that the resulting sysclk, platform, and e600 (core) frequencies do not exceed their respective maximum or minimum operating frequencies. refer to section 4.1.2 ?platform/mpx to sysclk pll ratio? on page 71 and section 4.1.3 ?e600 core to mpx/platform clock pll ratio? on page 72 , for ratio settings. 2. rise and fall times for sysclk are measured at 0.4v and 2.7v. 3. timing is guaranteed by design and characterization. 4. this represents the total input jitter, short term and long term, and is guaranteed by design. 5. the sysclk driver?s closed loop jitter bandwidth should be < 500 kh z at ?20 db. the bandwidth must be set low to allow cascade-connected pll-based devices to track sysclk drivers wi th the specified jitter. note that the frequency modulation for sysclk reduces significantly for the spread spectrum source case. this is to guarantee what is supported based on design. 3.4.1.1 sysclk and spre ad spectrum sources spread spectrum clock sources are a popular way to control electromagnetic interference emissions (emi) by spreading the emitted noise over a wider spectrum and reducing the peak noise magnitude. these clock sources intentionally add long-term jitter in order to diffuse the emi spectral content. the jit- ter specification given in table 3-9 considers short-term (cycle-to- cycle) jitter only and the clock generator?s cycle-to-cycle output jitter should meet t he pc8610 input cycle-to-cycle jitter requirement. frequency modulation and spread are separate concerns, and the pc8610 is compatible with spread spectrum sources if the recommendations listed in table 3-9 are observed. all specifications at recommended operating conditions (see table 3-2 on page 15 ). notes: 1. guaranteed by design. 2. sysclk frequencies resulting from frequency spreading, and the resulting core and vco frequencies, must meet the minimum and maxi mum specifications given in table 3-9 . it is imperative to note that the processor?s minimum and maximum sysclk, core, and vco frequen- cies must not be exceeded regardless of the type of clock source. therefore, systems in which the processor is operated at its maximum rated e600 core frequency should avoid violating the stated limits by using down-spreading only. table 3-8. sysclk ac timing specifications parameter/condition symbol min typical max unit notes sysclk frequency f sysclk 33 ? 133 mhz (1) sysclk cycle time t sysclk 7.5 ? ? ns ? sysclk rise and fall time t kh , t kl 0.6 1.0 1.2 ns (2) sysclk duty cycle t khk /t sysclk 40 ? 60 % (3) sysclk jitter ? ? ? 150 ps (4)(5) table 3-9. spread spectrum clock source recommendations parameter min max unit notes frequency modulation ? 50 khz (1) frequency spread ? 1.0 % (1)(2)
22 0926d?hirel?12/09 pc8610 [preliminary] e2v semiconductors sas 2009 sd n _ref_clk and sd n _ref_clk was designed to work with a spread spectrum clock (+0 to 0.5% spreading at 30-33khz rate is allowed), assuming both ends have same reference clock. for better results use a source without significant unintended modulation. 3.4.2 real time clock timing the rtc input is sampled by the platform clock. t he output of the sampling latch is then used as an input to the counters of the pic. there is no jitter specification. the minimum pulse width of the rtc sig- nal should be greater than 2 the period of the pla tform clock. that is, minimum clock high time is 2 t mpx , and minimum clock low time is 2 t mpx . there is no minimum rtc frequency; rtc may be grounded if not needed. 3.4.3 pci/pci-x reference clock timing when the pci/pci-x controller is configured for asynchronous operation, the reference clock for the pci/pci-x controller is not the sysclk input, but in stead the pcin_clk. provides the pci/pci-x refer- ence clock ac timing specifications for the pc8610. notes: 1. rise and fall times for sysclk are measured at 0.6v and 2.7v. 2. timing is guaranteed by design and characterization. 3.4.4 platform frequency requirements for pci-express and serial rapidio the mpx platform clock frequency must be considered for proper operation of the high-speed pci express and serial rapidio interfaces as described below. for proper pci express operation, the mpx clock frequency must be greater than or equal to: note that at mpx = 333 - 400 mhz, cfg_net2_div = 0 and at mpx > 400 mhz, cfg_net2_div = 1. there- fore, when operating pci express in x8 link width, the mpx platform frequency must be 333-400 mhz with cfg_net2_div = 0 or greater than or equal to 527 mhz with cfg_net2_div = 1. for proper serial rapidio operation, the mpx clock frequency must be greater than: 3.4.5 other input clocks for information on the in put clocks of other functional blocks of the platform such as serdes see the spe- cific section of this document. table 3-10. pci n_clk ac timing specifications parameter/condition symbol min typical max unit notes pcin_clk frequency f pciclk 16 ? 133 mhz ? pcin_clk cycle time t pciclk 7.5 ? 60 ns ? pcin_clk rise and fall time t pcikh , t pcikl 0.6 1.0 2.1 ns (1)(2) pcin_clk duty cycle t pcikhkl /t pciclk 40 ? 60 % (2) 527 mhz pci-express link width () 16 1 cfg_net2_div + () ? ----------------------------------------------------------------------------------------------- - 20.80 () (serial rapidio interface frequen cy) serial rapidio link width () 64 ------------------------------------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------
23 0926d?hirel?12/09 e2v semiconductors sas 2009 pc8610 [preliminary] 3.5 reset initialization table 3-11 describes the ac electrical specifications fo r the reset initialization timing requirements of the pc8610. notes: 1. sysclk is the primary clock input for the device. 2. this is related to hreset assertion time. table 3-12 provides the pll lock times. note: 1. the pll lock time for e600 pll requires an additional 255 platform clock cycles. 3.6 ddr and ddr2 sdram this section describes the dc and ac electrical specifications for the dd r sdram interface of the pc8610. note that ddr sdram is gv dd = 2.5v and ddr2 sdram is gv dd = 1.8v. 3.6.1 ddr sdram dc electrical characteristics table 3-13 provides the recommended operating conditions for the ddr2 sdram component(s) of the pc8610 when gv dd (typ) = 1.8v. table 3-11. reset initialization timing specifications parameter/condition min max unit notes required assertion time of hreset 100 ? s minimum assertion time for sreset 3 ? sysclks (1) platform pll input se tup time with stable sysclk before hreset negation 100 ? s (2) input setup time for por config s (other than pll config) with respect to negation of hreset 4 ? sysclks (1) input hold time for all por conf igs (including pll config) with respect to negation of hreset 2 ? sysclks (1) maximum valid-to-high impedance time for actively driven por configs with respect to negation of hreset ? 5 sysclks (1) table 3-12. pll lock times parameter/condition min max unit notes (platform, pci and e600 core) pll lock times ? 100 s (1) table 3-13. ddr2 sdram dc electrical characteristics for gv dd (typ) = 1.8v parameter/condition symbol min max unit notes i/o supply voltage gv dd 1.71 1.89 v (1) i/o reference voltage mv ref 0.49 gv dd 0.51 gv dd v (2) i/o termination voltage v tt mv ref ? 0.04 mv ref + 0.04 v (3) input high voltage v ih mv ref + 0.125 gv dd + 0.3 v input low voltage v il - 0.3 mv ref - 0.125 v
24 0926d?hirel?12/09 pc8610 [preliminary] e2v semiconductors sas 2009 note: 1. gv dd is expected to be within 50 mv of the dram gv dd at all times. 2. mv ref is expected to be equal to 0.5 gv dd , and to track gv dd dc variations as measured at the receiver. peak-to-peak noise on mv ref may not exceed 2% of the dc value. 3. v tt is not applied directly to the device. it is the supply to which far end signal termination is made and is expected to be equal to mv ref . this rail should track variations in the dc level of mv ref .. 4. output leakage is measured with all outputs disabled, 0v v out gv dd . table 3-14 provides the ddr capacitance when gv dd (typ) = 1.8v. note: 1. this parameter is sampled. gv dd = 1.8v 0.090v, f = 1 mhz, t a = 25 c, v out = gv dd /2, v out (peak-to- peak) = 0.2v. table 3-15 provides the recommended operating condit ions for the ddr sdram component(s) when gv dd (typ) = 2.5v. note: 1. gv dd is expected to be within 50 mv of the dram gv dd at all times. 2. mv ref is expected to be equal to 0.5 gv dd , and to track gv dd dc variations as measured at the receiver. peak-to-peak noise on mv ref may not exceed 2% of the dc value. 3. v tt is not applied directly to the device. it is the supply to which far end signal termination is made and is expected to be equal to mv ref . this rail should track variations in the dc level of mv ref . 4. output leakage is measured with all outputs disabled, 0v v out gv dd . output leakage current i oz - 50 50 a (4) output high current (v out = 1.420v) i oh - 13.4 ? ma output low current (v out = 0.280v) i ol 13.4 ? ma table 3-14. ddr2 sdram capacitance for gv dd (typ) = 1.8v parameter/condition symbol min max unit notes input/output capacita nce: dq, dqs, dqs c io 68pf (1) delta input/output capacitance: dq, dqs, dqs c dio ?0.5pf (1) table 3-15. ddr sdram dc electrical characteristics for gv dd (typ) = 2.5v parameter/condition symb ol min max unit notes i/o supply voltage gv dd 2.375 2.625 v (1) i/o reference voltage mv ref 0.49 gv dd 0.51 gv dd v (2) i/o termination voltage v tt mv ref ? 0.04 mv ref + 0.04 v (3) input high voltage v ih mv ref + 0.15 gv dd + 0.3 v input low voltage v il ?0.3 mv ref - 0.15 v output leakage current i oz ?50 50 a (4) output high current (v out = 1.95v) i oh ?16.2 ? ma output low current (v out = 0.35v) i ol 16.2 ? ma table 3-13. ddr2 sdram dc electrical characteristics for gv dd (typ) = 1.8v (continued) parameter/condition symbol min max unit notes
25 0926d?hirel?12/09 e2v semiconductors sas 2009 pc8610 [preliminary] table 3-16 provides the ddr capacitance when gv dd (typ) = 2.5v. note: 1. this parameter is sampled. gv dd = 2.5v 0.125v, f = 1 mhz, t a = 25 c, v out = gv dd /2, v out (peak-to-peak) = 0.2v. table 3-17 provides the current draw characteristics for mv ref . note: 1. the voltage regulator for mv ref must be able to supply up to 500 a current. 3.6.2 ddr sdram ac electrical characteristics this section provides the ac electrical char acteristics for the ddr/ddr2 sdram interface. 3.6.2.1 ddr sdram input ac timing specifications table 3-18 provides the input ac timing specif ications for the ddr2 sdram when gv dd (typ) = 1.8v. table 3-19 provides the input ac timing spec ifications for the ddr sdram when gv dd (typ) = 2.5v. table 3-16. ddr sdram capacitance for gv dd (typ) = 2.5v parameter/condition symbol min max unit notes input/output capacitance: dq, dqs c io 68pf (1) delta input/output capacitance: dq, dqs c dio ?0.5pf (1) table 3-17. current draw characteristics for mv ref parameter/condition symbol min max unit note current draw for mv ref i mvref ?500a (1) table 3-18. ddr2 sdram input ac timing specifications for 1.8v interface (at recommended operating conditions) parameter symbol min max unit ac input low voltage v il ? mv ref - 0.25 v ac input high voltage v ih mv ref + 0.25 ? v table 3-19. ddr sdram input ac timing specifications for 2.5v interface (at recommended oper- ating conditions) parameter symbol min max unit ac input low voltage v il ? mv ref - 0.31 v ac input high voltage v ih mv ref + 0.31 v
26 0926d?hirel?12/09 pc8610 [preliminary] e2v semiconductors sas 2009 table 3-20 provides the input ac timing specif ications for the ddr sdram interface. notes: 1. t ciskew represents the total amount of skew consumed by the controller between mdqs[n] and any cor- responding bit that will be captured with mdqs[n]. this should be subtracted from the total timing budget. 2. the amount of skew that can be tolerated from mdqs to a corresponding mdq signal is called t diskew .this can be determined by the following equation: t diskew = (t/4 - abs( t ciskew )) where t is the clock period and abs( t ciskew ) is the absolute value of t ciskew . 3. maximum ddr1 frequency is 400 mhz, minimum ddr2 frequency is 400 mhz. figure 3-3 shows the ddr sdram input timing for the mdqs to mdq skew measurement (t diskew ). figure 3-3. ddr input timing diagram for t diskew table 3-20. ddr sdram input ac timing specifications (at recommended operating conditions) parameter symbol min max unit notes controller skew for mdqs ? mdq/mecc t ciskew ps (1)(2) 533 mhz ? 300 300 (3) 400 mhz ? 365 365 333 mhz ? 390 390 mck[n] mck[n] t mck mdq[x] mdqs[n] t diskew d1 d0 t diskew
27 0926d?hirel?12/09 e2v semiconductors sas 2009 pc8610 [preliminary] 3.6.2.2 ddr sdram output ac timing specifications notes: 1. the symbols used for timing specifications follow the pattern of t (first two letters of functional block)(signal)(state) (reference)(state) for inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. output hold time can be read as ddr timing (dd) from the rising or falling edge of the reference clock (kh or kl) until the output went invalid (ax or dx). for example, t ddkhas symbol- izes ddr timing (dd) for the time t mck memory clock reference (k) goes from the high (h) state until outputs (a) are setup (s) or output valid time. also, t ddkldx symbolizes ddr timing (dd) for the time t mck memory clock reference (k) goes low (l) until data outputs (d) are invalid (x) or data output hold time. 2. all mck/mck referenced measurements are made from the crossing of the two signals 0.1v. 3. addr/cmd includes all ddr sdram output signals except mck /mck , mcs, and mdq/mecc/mdm/mdqs. table 3-21. ddr sdram output ac timing specificatio ns (at recommended operating conditions) parameter symbol (1) min max unit notes mck[n] cycle time, mck[n]/mck [n] crossing t mck 310ns (2) mck duty cycle 533 mhz 400 mhz 333 mhz t mckh /t mck 47 47 47 53 53 53 % (8) (8) addr/cmd output setup with respect to mck 533 mhz 400 mhz 333 mhz t ddkhas 1.48 1.95 2.40 ? ? ? ns (3) (7) addr/cmd output hold with respect to mck 533 mhz 400 mhz 333 mhz t ddkhax 1.48 1.95 2.40 ? ? ? ns (3) (7) mcs [n] output setup with respect to mck 533 mhz 400 mhz 333 mhz t ddkhcs 1.48 1.95 2.40 ? ? ? ns (3) (7) mcs [n] output hold with respect to mck 533 mhz 400 mhz 333 mhz t ddkhcx 1.48 1.95 2.40 ? ? ? ns (3) (7) mck to mdqs skew t ddkhmh ?0.6 0.6 ns (4) mdq/mecc/mdm output set up with respect to mdqs 533 mhz 400 mhz 333 mhz t ddkhds , t ddklds 590 700 900 ? ? ? ps (5) (7) mdq/mecc/mdm output hold with respect to mdqs 533 mhz 400 mhz 333 mhz t ddkhdx , t ddkldx 590 700 900 ? ? ? ps (5) (7) mdqs preamble start t ddkhmp ?0.5 t mck - 0.6 ?0.5 t mck + 0.6 ns (6) mdqs epilogue end t ddkhme ?0.6 0.6 ns (6)
28 0926d?hirel?12/09 pc8610 [preliminary] e2v semiconductors sas 2009 4. note that t ddkhmh follows the symbol conventions described in note 1. for example, t ddkhmh describes the ddr timing (dd) from the rising edge of the mck[n] clock (k h) until the mdqs signal is valid (mh). t ddkhmh can be modified through control of the dqss override bits in the timing_cfg_2 register. this will typically be set to the same delay as the clock adjust in the clk_cntl register. the timing parameters listed in the ta ble assume that these 2 parameters have been set to the same adjustment value. see the pc8610 integrated host proc essor reference manual for a description and understanding of the timing modifications enabled by use of these bits. 5. determined by maximum possible skew between a data st robe (mdqs) and any corresponding bit of data (mdq), ecc (mecc), or data mask (mdm). the data strobe should be centered inside of the data eye at the pins of the microprocessor. 6. all outputs are referenced to the rising edge of mck[ n] at the pins of the microprocessor. note that t ddkhmp follows the sym- bol conventions described in note 1. 7. maximum ddr1 frequency is 400 mhz, minimum ddr2 frequency is 400 mhz. 8. per the jedec spec the ddr2 duty cycle at 400 and 533 mhz is the low and high cycle time values. note: for the addr/cmd setup and hold specifications in table 3-21 on page 27 , it is assumed that the clock control register is set to adjust the memory clocks by 1/2 applied cycle. figure 3-4 shows the ddr sdram output timing for the mck to mdqs skew measurement (t ddkhmh ). figure 3-4. timing diagram for t ddkhmh mdqs mck[n] mck[n] t mck mdqs t ddkhmh(max) = 0.6 ns t ddkhmh(min) = -0.6 ns
29 0926d?hirel?12/09 e2v semiconductors sas 2009 pc8610 [preliminary] figure 3-5 shows the ddr sdram output timing diagram. figure 3-5. ddr sdram output timing diagram figure 3-6 provides the ac test load for the ddr bus. figure 3-6. ddr ac test load addr/cmd t ddkhas , t ddkhcs t ddkhmh t ddklds t ddkhds mdq[x] mdqs[n] mck[n] mck[n] t mck t ddkldx t ddkhdx d1 d0 t ddkhax , t ddkhcx write a0 noop t ddkhmp t ddkhme output z 0 = 50 gv dd /2 r l = 50
30 0926d?hirel?12/09 pc8610 [preliminary] e2v semiconductors sas 2009 3.7 local bus this section describes the dc and ac electrical spec ifications for the local bus interface of the pc8610. 3.7.1 local bus dc electrical characteristics table 3-22 provides the dc electrical characteristics for the local bus interface operating at bv dd = 3.3v. note: 1. the symbol v in , in this case, represents the bv in symbol referenced in table 3-1 on page 14 and table 3-2 on page 15 . table 3-23 provides the dc electrical characteristics for the local bus interface operating at bv dd =2.5vdc. note: 1. the symbol v in , in this case, represents the bv in symbol referenced in table 3-1 on page 14 and table 3-2 on page 15 . table 3-22. local bus dc electrical characteristics (bv dd = 3.3v dc) parameter symbol min max unit high-level input voltage v ih 2bv dd + 0.3 v low-level input voltage v il ?0.3 0.8 v input current (v in (1) = 0v or v in = bv dd ) i in ? 5a high-level output voltage (bv dd = min, i oh = ?2 ma) v oh bv dd ? 0.2 ? v low-level output voltage (bv dd = min, i ol = 2 ma) v ol ?0.2v table 3-23. local bus dc electrical characteristics (bv dd = 2.5v dc) parameter symbol min max unit high-level input voltage v ih 1.70 bv dd + 0.3 v low-level input voltage v il ?0.3 0.7 v input current (v in (1) = 0v or v in = bv dd ) i in ? 15 a high-level output voltage (bv dd = min, i oh = ?1 ma) v oh 2.0 ? v low-level output voltage (bv dd = min, i ol = 1 ma) v ol ?0.4v
31 0926d?hirel?12/09 e2v semiconductors sas 2009 pc8610 [preliminary] table 3-24 provides the dc electrical characteristics for the local bus interface operating at bv dd =1.8v note: 1. the symbol v in , in this case, represents the bv in symbol referenced in table 3-1 on page 14 and table 3-2 on page 15 . 3.7.2 local bus ac electrical specifications table 3-25 describes the general timing parameters of the local bus interface at bv dd = 3.3v. for infor- mation about the frequency range of local bus see section 4.1.1 ?clock ranges? on page 70 . table 3-24. local bus dc electrical characteristics (bv dd = 1.8v dc) parameter symbol min max unit high-level input voltage v ih 1.3 bv dd + 0.3 v low-level input voltage v il ?0.3 0.8 v input current (v in (1) = 0v or v in = bv dd ) i in ?15a high-level output voltage ( bv dd = min, i oh = ?1 ma) v oh 1.42 ? v low-level output voltage ( bv dd = min, i ol = 1 ma) v ol ?0.2v table 3-25. local bus timing parameters (bv dd = 3.3v, 2.5v and 1.8v) parameter symbol (1) min max unit notes local bus cycle time t lbk 7.5 ? ns local bus duty cycle t lbkh /t lbk 45 55 % lclk[n] skew to lclk[m] t lbkskew ? 100 ps (2)(7) input setup to local bus clock (except lgta /lupwait) t lbivkh1 4.5 ? ns (3)(4) lgta /lupwait input setup to local bus clock t lbivkl2 4.3 ? ns (3)(4) input hold from local bus clock (except lgta /lupwait) t lbixkh1 ?0.8ns (3)(4) lgta /lupwait input hold from local bus clock t lbixkl2 ?0.7ns (3)(4) lale output transition to lad/ldp output transition (latch hold time) t lbotot 0.75 ? ns (5) local bus clock to output valid (except lad/ldp and lale) t lbklov1 ? 1.1 ns local bus clock to data valid for lad/ldp t lbklov2 ?1.2 ns (3) local bus clock to address valid for lad, and lale t lbklov3 ?1.2 ns (3) local bus clock to lale assertion t lbklov4 ? 1.4 ns output hold from local bus clock (except lad/ldp and lale) t lbklox1 ?0.6 ? ns (3)
32 0926d?hirel?12/09 pc8610 [preliminary] e2v semiconductors sas 2009 notes: 1. the symbols used for timing sp ecifications follow the pattern of t (first two letters of functional block)(signal)(state)(refer- ence)(state) for inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. for example, t lbixkh1 symbolizes local bus timing (lb) for the input (i) to go invalid (x) with respect to the time the t lbk clock reference (k) goes high (h), in this case for clock one(1). also, t lbkhox symbolizes local bus timing (lb) for the t lbk clock reference (k) to go high (h), with respect to the output (o) going invalid (x) or out- put hold time. 2. maximum possible clock skew between a clock lclk[m] and a relative clock lclk[n]. skew measured between complementary signals at bv dd /2. skew number is valid only when lclk[m] and lclk[n] have the same load. 3. all signals are measured from bv dd /2 of the edge of local bus clock to 0.4 bv dd of the signal in ques- tion for 3.3v signaling levels. 4. input timings are measured at the pin. 5. the value of t lbotot is the measurement of the minimum time between the negation of lale and any change in lad. 6. for purposes of active/float timing measurements, th e hi-z or off state is defined to be when the total current delivered through the component pin is less than or equal to the leakage current specification. 7. guaranteed by design. figure 3-7 provides the ac test load for the local bus. figure 3-7. local bus ac test load figure 3-8 to figure 3-10 on page 35 show the local bus signals. note: output signals are latched at the falling edge of lclk and input signals are captured at the rising edge of lclk, with the exception of the lgta /lupwait signal, which is captured at the falling edge of lclk. output hold from local bus clock for lad/ldp t lbklox2 ?0.6 ? ns (3) local bus clock to output high impedance (except lad/ldp and lale) t lbkloz1 ?2.5 ns (6) local bus clock to output high impedance for lad/ldp t lbkloz2 ?2.5 ns (6) table 3-25. local bus timing parameters (bv dd = 3.3v, 2.5v and 1.8v) (continued) parameter symbol (1) min max unit notes bv dd /2 output z 0 = 50 r l = 50
33 0926d?hirel?12/09 e2v semiconductors sas 2009 pc8610 [preliminary] figure 3-8. local bus signals output signals: la[27:31]/lbctl/lbcke/loe / lfcle/lfale/lfre / lfwp /llwe t lbklov2 lclk[n] input signals: lad[0:31]/ldp[0:3] output (data) signals: lad[0:31]/ldp[0:3] lale t lbixkh1 input signal: lgta output (address) signal: lad[0:31] t lbivkh1 t lbixkl2 t lbivkl2 t lbklox1 t lbkloz2 t lbotot t lbklox2 t lbklov1 t lbklov3 t lbkloz1 t lbklov4 lupwait
34 0926d?hirel?12/09 pc8610 [preliminary] e2v semiconductors sas 2009 figure 3-9. local bus signals, gpcm/upm/fcm signals for lcrr[clkdiv] = 2 (clock ratio of 4) t lbivkh1 t lbixkl2 upm mode input signal: lupwait t1 t3 input signals: lad[0:31]/ldp[0:3] upm mode output signals: lcs [0:7]/lbs [0:3]/lgpl[0:5] mode output signals: lcs [0:7]/lwe t lbklov1 t lbkloz1 lclk t lbklox1 t lbixkh1 gpcm mode input signal: lgta t lbivkl2 gpcm/fcm
35 0926d?hirel?12/09 e2v semiconductors sas 2009 pc8610 [preliminary] figure 3-10. local bus signals, gpcm/upm/fcm signals for lcrr[clkdiv] = 4 or 8 (clock ratio of 8 or 16) 3.8 display interface unit this section describes the diu dc and ac electrical specifications. 3.8.1 diu dc electrical characteristics table 3-26 provides the diu dc electrical characteristics. note: 1. note that the symbol v in , in this case, represents the ov in symbol referenced in table 3-1 on page 14 and table 3-2 on page 15 . t lbixkl2 t lbivkh1 upm mode input signal: lupwait t1 t3 upm mode output signals: lcs [0:7]/lbs [0:3]/lgpl[0:5] mode output signals: lcs [0:7]/lwe t2 t4 input signals: lad[0:31]/ldp[0:3] lclk t lbklov1 t lbkloz1 t lbklox1 t lbixkh1 gpcm mode input signal: lgta t lbivkl2 gpcm/fcm table 3-26. diu dc electrical characteristics parameter symbol min max unit high-level input voltage v ih 2 ov dd + 0.3 v low-level input voltage v il ?0.3 0.8 v input current (v in (1) = 0v or v in = v dd i in ?5a high-level output voltage (ov dd = min, i oh = ?100 a) v oh ov dd - 0.2 ? v low-level output voltage (ov dd = min, i ol = 100 a) v ol ?0.2 v
36 0926d?hirel?12/09 pc8610 [preliminary] e2v semiconductors sas 2009 3.8.2 diu ac timing specifications figure 3-11 depicts the horizontal timing (timing of one line), including both the horizontal sync pulse and the data. all parameters shown in the diagram are programmable. this timing diagram corresponds to positive polarity of the diu_clk_out signal and ac tive-high polarity of the diu_hsync, diu_vsync and diu_de signals. by default, all control signals and the display data are generated at the rising edge of the internal pixel clock, and the diu_clk_out output to drive the panel has the same polarity with the internal pixel clock. user ca n select the polarity of the diu_ hsync and diu_vsync signal (via the syn_pol register), whether active-high or active-low, the default is active-high. the diu_de signal is always active-high. figure 3-11. tft diu/lcd interface timing dia gram - horizontal sync pulse figure 3-12 depicts the vertical timing (timing of one frame), including both the vertical sync pulse and the data. all parameters shown in the diagram are programmable. 1 23 delta_x t pwh t bph t sw t fph diu_clk_out diu_ld diu_hsync diu_de t pcp 1 invalid data invalid data start of line t hsp
37 0926d?hirel?12/09 e2v semiconductors sas 2009 pc8610 [preliminary] figure 3-12. tft diu/lcd interface timing dia gram - vertical sync pulse table 3-27 shows timing parameters of signals presented in figure 3-11 on page 36 and figure 3-12 on page 37 . notes: 1. display interface pixel clock period immediate value (in nanosecond). 2. display pixel clock frequency must also be less than or equal to 1/3 the platform clock. the delta_x and delta_y parameters are programmed via the disp_size register; the pw_h, bp_h, and fp_h parameters are programmed vi a the hsyn_para register ; and the pw_v, bp_v and fp_v parameters are programmed via the vsyn_para register. figure 3-13 depicts the synchronous display interf ace timing for access level, and table 3-28 lists the timing parameters. 1 23 delta_y t pwv t bpv t sh t fpv diu_hsync diu_ld diu_vsync diu_de t hsp 1 (line data) start of frame invalid data invalid data t vsp table 3-27. diu interface ac timing parameters - pixel level parameter symbol value unit notes display pixel clock period t pcp 7.5 (minimum) ns (1)(2) hsync width t pwh pw_h * t pcp ns hsync back porch width t bph bp_h * t pcp ns hsync front porch width t fph fp_h * t pcp ns screen width t sw delta_x * t pcp ns hsync (line) period t hsp (pw_h + bp_h + delta_x + fp_h) * t pcp ns vsync width t pwv pw_v * t hsp ns hsync back porch width t bpv bp_v * t hsp ns hsync front porch width t fpv fp_v * t hsp ns screen height t sh delta_y * t hsp ns vsync (frame) period t vsp (pw_v + bp_v + delta_y + fp_h) * t hsp ns
38 0926d?hirel?12/09 pc8610 [preliminary] e2v semiconductors sas 2009 figure 3-13. lcd interface timing diagram - access level note: the diu_out_clk edge and phase delay is sele ctable via the global utilities ckdvdr register. 3.9 i 2 c this section describes the dc and ac electrical characteristics for the i 2 c interfaces of the pc8610. 3.9.1 i 2 c dc electrical characteristics table 3-45 provides the dc electrical characteristics for the i 2 c interfaces. notes: 1. output voltage (open drain or open co llector) condition = 3 ma sink current. 2. refer to the pc8610 integrated host processor refere nce manual for information on the digital filter used. 3. i/o pins will obstruct the sda and scl lines if ov dd is switched off. table 3-28. lcd interface timing parameters - access level parameter symbol min typ max unit lcd interface pixel clock high time t ckh 0.35* t pcp 0.5* t pcp 0.65* t pcp ns lcd interface pixel clock low time t ckl 0.35* t pcp 0.5* t pcp 0.65* t pcp ns lcd interface pixel clock to ouput valid t diukhov ??2 ns lcd interface output hold from pixel clock t diukhox t pcp - 2 ? ? ns t ckh diu_hsync diu_vsync diu_de diu_clk_out t diukhov t ckl diu_ld t diukhox table 3-29. i 2 c dc electrical characteristics (at recommended operating conditions with ov dd of 3.3v 5%) parameter symbol min max unit notes input high voltage level v ih 0.7 ov dd ov dd +0.3 v input low voltage level v il ?0.3 0.3 .ov dd v low level output voltage v ol 0 0.2 .ov dd v (1) pulse width of spikes which must be suppressed by the input filter t i2khkl 050ns (2) input current each i/o pin (input voltage is between 0.1 ov dd and 0.9 ov dd (max) i i ?10 10 a (3) capacitance for each i/o pin c i ?10pf
39 0926d?hirel?12/09 e2v semiconductors sas 2009 pc8610 [preliminary] 3.9.2 i 2 c ac electrical specifications table 3-30 provides the ac timing parameters for the i 2 c interfaces. notes: 1. the symbols used for timing specifications herein follow the pattern of t (first two letters of functional bl ock)(signal)(state) (reference)(state) for inputs and t (first two letters of functional bl ock)(reference)(state)(signal)(state) for outputs. for example, t i2dvkh symbolizes i 2 c timing (i2) with respect to the time data input signals (d) reach the valid state (v) relative to the t i2c clock reference (k) going to the high (h) state or setup time. also, t i2sxkl symbolizes i 2 c timing (i2) for the time that the data with respect to the start condition (s) went invalid (x) relative to the t i2c clock reference (k) going to the low (l) state or hold time. also, t i2pvkh symbolizes i 2 c tim- ing (i2) for the time that the data with respect to the stop condition (p) reaching the valid state (v) relative to the t i2c clock reference (k) going to the high (h) state or setup time. for rise and fall times, the latter convention is used with the approp ri- ate letter: r (rise) or f (fall). 2. as a transmitter, the pc8610 provides a delay time of at least 300 ns for the sda signal (referred to the v ihmin of the scl sig- nal) to bridge the undefined region of the falling edge of sc l to avoid unintended generation of start or stop condition. when pc8610 acts as the i 2 c bus master while transmitting, pc8610 drives both scl and sda. as long as the load on scl and sda are balanced, pc8610 would not cause unintended genera tion of start or stop condition. therefore, the 300 ns sda output delay time is not a concern. if, under some rare condition, the 300 ns sda output delay time is required for pc8610 as transmitter, the following setting is recommended for the fdr bit field of the i2cfdr register to ensure both the desired i 2 c scl clock frequency and sda output delay time are achieved, assuming that the desired i 2 c scl clock fre- quency is 400 khz and the digital filter sampling rate register (i2cdfsrr) is programmed wit h its default setting of 0x10 (decimal 16): i 2 c source clock frequency 533 mhz 400 mhz 333 mhz 266 mhz fdr bit setting 0x0a 0x07 0x2a 0x05 actual fdr divider selected 1536 1024 896 704 actual i 2 c scl frequency generated 347 khz 391 khz 371 khz 378 khz for the detail of i 2 c frequency calculation, refer to the application note an2919 ?determining the i 2 c frequency divider ratio for scl?. note that the i 2 c source clock frequency is equal to the mpx clock frequency for pc8610. 3. the maximum t i2dxkl has only to be met if the device does not stretch the low period (t i2cl ) of the scl signal. 4. c b = capacitance of one bus line in pf. 5. guaranteed by design. table 3-30. i 2 c ac electrical specifications (all values refer to v ih (min) and v il (max) levels. see table 3-29 ). parameter symbol (1) min max unit scl clock frequency f i2c 0 400 khz low period of the scl clock t i2cl (5) 1.3 ? s high period of the scl clock t i2ch (5) 0.6 ? s setup time for a repeated start condition t i2svkh (5) 0.6 ? s hold time (repeated) start condition (after this period, the first clock pulse is generated) t i2sxkl (5) 0.6 ? s data setup time t i2dvkh (5) 100 ? ns data input hold time: - cbus compatible masters - i 2 c bus devices t i2dxkl ? 0 (2) ? ? s data ouput delay time t i2ovkl ?0.9 (3) s rise time of both sda and scl signals t i2cr 20 + 0.1 c b (4) 300 ns fall time of both sda and scl signals t i2cf 20 + 0.1 c b (4) 300 ns set-up time for stop condition t i2pvkh 0.6 ? s bus free time between a stop and start condition t i2khdx 1.3 ? s noise margin at the low level for each connected device (inc luding hysteresis) v nl 0.1 ov dd ?v noise margin at the high level for eac h connected device (including hysteresis) v nh 0.2 ov dd ?v
40 0926d?hirel?12/09 pc8610 [preliminary] e2v semiconductors sas 2009 figure 3-14 provides the ac test load for the i 2 c figure 3-14. i 2 c ac test load figure 3-15 shows the ac timing diagram for the i 2 c bus. figure 3-15. i 2 c bus ac timing diagram 3.10 duart this section describes the dc and ac electrical s pecifications for the duart interface of the pc8610. 3.10.1 duart dc electrical characteristics table 3-31 provides the dc electrical char acteristics for t he duart interface. note: 1. note that the symbol v in , in this case, represents the ov in symbol referenced in table 3-1 on page 14 and table 3-2 on page 15 . output z 0 = 50 ov dd /2 r l = 50 sr s sda scl t i2cf t i2cl t i2sxkl t i2dxkl t i2dvkh t i2ch t i2sxkl ps t i2cf t i2cr t i2pvkh t i2svkh t i2khkl table 3-31. duart dc electrical characteristics parameter symbol min max unit high-level input voltage v ih 2ov dd + 0.3 v low-level input voltage v il ?0.3 0.8 v input current ( v in (1) = 0v or v in = v dd ) i in ? 5 a high-level output voltage (ov dd = min, i oh = ?100 a) v oh ov dd - 0.2 ? v low-level output voltage (ov dd = min, i ol = 100 a) v ol ? 0.2 v
41 0926d?hirel?12/09 e2v semiconductors sas 2009 pc8610 [preliminary] 3.10.2 duart ac electrical specifications table 3-32 provides the ac timing parameters for the duart interface. notes: 1. guaranteed by design. 2. actual attainable baud rate will be limited by the latency of interrupt processing. 3. the middle of a start bit is detected as the 8 th sampled 0 after the 1-to-0 transition of the start bit. sub- sequent bit values are sampled each 16 th sample. 3.11 fast/serial infrared interfaces (firi/siri) the fast/serial infrared interfaces (firi/siri) implements asynchronous infrared protocols (fir, mir, sir) that are defined by irda ? (infrared data association). refer to http://www.irda.org for details on fir and sir protocols. 3.12 synchronous serial interface (ssi) this section describes the dc and ac electrical specifications for the ssi interface of the pc8610. 3.12.1 ssi dc electrical characteristics table 3-33 provides ssi dc electrical characteristics. note: 1. note that the symbol bv in , in this case, represents the bv in symbol referenced in table 3-1 on page 14 and table 3-2 on page 15 . table 3-32. duart ac timing specifications parameter value unit notes minimum baud rate platform clock/1,048,576 baud (1) maximum baud rate platform clock/16 baud (1)(2) oversample rate 16 ? (1)(3) table 3-33. ssi dc electrical characteristics (3.3v dc) parameter symbol min max unit high-level input voltage v ih 2bv dd + 0.3 v low-level input voltage v il ?0.3 0.8 v input current (bv in (1) = 0v or bv in = bv dd ) i in ?5a high-level output voltage (b v dd = min, i oh = ?2 ma) v oh bv dd - 0.2 ?v low-level output voltage (bv dd = min, i ol = 2 ma) v ol ?0.2v
42 0926d?hirel?12/09 pc8610 [preliminary] e2v semiconductors sas 2009 3.12.2 ssi ac timing specifications all timings for the ssi are given for a non-inverted serial clock polarity (tsckp/rsckp = 0) and a non- (tfsi/rfsi = 0). if the polarity of the clock and/or the frame sync have been inverted, all the timing remains valid by inverting the clock signal stck/srck and/or the frame sync stfs/srfs shown in the following tables and figures. for internal frame sync operation us ing external clock, the fs timing will be same as that of tx data. 3.12.2.1 ssi transmitter timing with internal clock table 3-34 provides the transmitter timing parameters with internal clock. table 3-34. ssi transmitter with internal clock timing parameters parameter symbol min max unit internal clock operation (tx/rx) ck clock period ss1 81.4 ? ns (tx/rx) ck clock high period ss2 36.0 ? ns (tx/rx) ck clock rise time ss3 ? 6 ns (tx/rx) ck clock low period ss4 36.0 ? ns (tx/rx) ck clock fall time ss5 ? 6 ns (tx) ck high to fs high ss10 ? 15.0 ns (tx) ck high to fs low ss12 ? 15.0 ns (tx/rx) internal fs rise time ss14 ? 6 ns (tx/rx) internal fs fall time ss15 ? 6 ns (tx) ck high to stxd valid from high impedance ss16 ? 15.0 ns (tx) ck high to stxd high/low ss17 ? 15.0 ns (tx) ck high to stxd high impedance ss18 ? 15.0 ns stxd rise/fall time ss19 ? 6 ns synchronous internal clock operation srxd setup before (tx) ck falling ss42 10.0 ? ns srxd hold after (tx) ck falling ss43 0 ? ns loading ss52 ? 25 pf
43 0926d?hirel?12/09 e2v semiconductors sas 2009 pc8610 [preliminary] figure 3-16 provides the ssi transmitter timing with internal clock. figure 3-16. ssi transmitter with internal clock timing diagram note: srxd input in synchronous mode only 3.12.2.2 ssi receiver timing with internal clock table 3-35 provides the receiver timing parameters with internal clock. ss19 ssin_tck ssin_tfs ss1 ssin_txd ssin_rxd ss2 ss4 ss3 ss5 ss10 ss12 ss14 ss18 ss15 ss17 ss16 ss43 ss42 (output) (output) (output) (input) table 3-35. ssi receiver with internal clock timing parameters parameter symbol min max unit internal clock operation (tx/rx) ck clock period ss1 81.4 ? ns (tx/rx) ck clock high period ss2 36.0 ? ns (tx/rx) ck clock rise time ss3 ? 6 ns (tx/rx) ck clock low period ss4 36.0 ? ns (tx/rx) ck clock fall time ss5 ? 6ns (rx) ck high to fs high ss11 ? 15.0 ns (rx) ck high to fs low ss13 ? 15.0 ns srxd setup time before (rx) ck low ss20 10.0 ? ns srxd hold time after (rx) ck low ss21 0 ? ns
44 0926d?hirel?12/09 pc8610 [preliminary] e2v semiconductors sas 2009 figure 3-20 provides the ssi receiver timing with internal clock. figure 3-17. ssi receiver with internal clock timing diagram 3.12.2.3 ssi transmitter timing with external clock table 3-36 provides the transmitter timing parameters with external clock. ssin_tck ssin_rfs ssin_rxd ss1 ss4 ss2 ss20 ss21 ss11 ss13 (output) (output) (input) ss3 ss5 table 3-36. ssi transmitter with external clock timing parameters parameter symbol min max unit external clock operation (tx/rx) ck clock period ss22 81.4 ? ns (tx/rx) ck clock high period ss23 36.0 ? ns (tx/rx) ck clock rise time ss24 ? 6.0 ns (tx/rx) ck clock low period ss25 36.0 ? ns (tx/rx) ck clock fall time ss26 ? 6.0 ns (tx) ck high to fs high ss31 ?10.0 15.0 ns (tx) ck high to fs low ss33 10.0 ? ns (tx) ck high to stxd valid from high impedance ss37 ? 15.0 ns (tx) ck high to stxd high/low ss38 ? 15.0 ns (tx) ck high to stxd high impedance ss39 ? 15.0 ns synchronous external clock operation srxd setup before (tx) ck falling ss44 10.0 ? ns srxd hold after (tx) ck falling ss45 2.0 ? ns srxd rise/fall time ss46 ? 6.0 ns
45 0926d?hirel?12/09 e2v semiconductors sas 2009 pc8610 [preliminary] figure 3-18 provides the ssi transmitter timing with external clock. figure 3-18. ssi transmitter with external clock timing diagram note: srxd input in synchronous mode only 3.12.2.4 ssi receiver ti ming with external clock figure 3-37 provides the receiver timing parameters with external clock. ss45 ss33 ss24 ss26 ss25 ss23 ssin_tck ssin_tfs ssin_txd ssin_rxd ss31 ss22 ss44 ss39 ss38 ss37 ss46 (input) (input) (output) (input) table 3-37. ssi receiver with external clock timing parameters parameter symbol min max unit external clock operation (tx/rx) ck clock period ss22 81.4 ? ns (tx/rx) ck clock high period ss23 36.0 ? ns (tx/rx) ck clock rise time ss24 ? 6.0 ns (tx/rx) ck clock low period ss25 36.0 ? ns (tx/rx) ck clock fall time ss26 ? 6.0 ns (rx) ck high to fs high ss32 ? 10.0 15.0 ns (rx) ck high to fs low ss34 10.0 ? ns (tx/rx) external fs rise time ss35 ? 6.0 ns (tx/rx) external fs fall time ss36 ? 6.0 ns srxd setup time before (rx) ck low ss40 10.0 ? ns srxd hold time after (rx) ck low ss41 2.0 ? ns
46 0926d?hirel?12/09 pc8610 [preliminary] e2v semiconductors sas 2009 table 3-22 provides the ssi receiver timing with external clock. figure 3-19. ssi receiver with external clock timing diagram 3.13 global timer module this section describes the dc and ac electrical s pecifications for the global timer module of the pc8610. 3.13.1 gtm dc electrical characteristics table 3-38 provides the dc electrical characteristics for the pc8610 global timer module pins, including gtmn_tinn, gtmn_tout n, gtmn_tgate n, and rtc. note: 1. note that the symbol v in , in this case, represents the ov in symbol referenced in table 3-1 on page 14 and table 3-2 on page 15 . ss24 ss34 ss35 ss26 ss25 ss23 ssin_tck ssin_rfs ssin_rxd ss40 ss22 ss32 ss36 ss41 (input) (input) (input) table 3-38. gtm dc electrical characteristics parameter symbol min max unit high-level input voltage v ih 2ov dd + 0.3 v low-level input voltage v il ? 0.3 0.8 v input current (v in (1) = 0v or v in = v dd ) i in ? 5 a high-level output voltage (ov dd = min, i oh = ? 100 a) v oh ov dd ? 0.2 ? v low-level output voltage (ov dd = min, i ol = 100 a) v ol ? 0.2 v
47 0926d?hirel?12/09 e2v semiconductors sas 2009 pc8610 [preliminary] 3.13.2 gtm ac timing specifications table 3-39 provides the gtm input and out put ac timing specifications. notes: 1. input specifications are measured from the 50 perce nt level of the signal to the 50 percent level of the rising edge of clkin. timings are measured at the pin. 2. timer inputs and outputs are asynchronous to any vi sible clock. timer outputs should be synchronized before use by external synchronous logic. timer inputs are required to be valid for at least t gtiwid ns to ensure proper operation. 3. the minimum pulse width is a function of the mpx/ platform clock. the minimum pulse width must be greater than or equal to 4 times the mpx/platform clock period. figure 3-20 provides the ac test load for the gtm figure 3-20. gtm ac test load 3.14 gpio this section describes the dc and ac electric al specifications for the gpio of the pc8610. 3.14.1 gpio dc electrical characteristics table 3-40 provides the dc electrical characteristics for the gpio. note: 1. note that the symbol v in , in this case, represents the ov in symbol referenced in table 3-1 on page 14 and table 3-2 on page 15 . table 3-39. gtm input and output ac timing specifications (1) characteristic symbol (2) min unit notes gtm inputs: minimum pulse width t gtiwid 7.5 ns (3) gtm outputs: minimum pulse width t gtowid 12 ns output z 0 = 50 ov dd /2 r l = 50 table 3-40. gpio dc electrical characteristics parameter symbol min max unit high-level input voltage v ih 2ov dd + 0.3 v low-level input voltage v il ? 0.3 0.8 v input current (v in (1) = 0v or v in = v dd ) i in ? 5 a high-level output voltage (ov dd = min, i oh = ? 100 a) v oh ov dd ? 0.2 ? v low-level output voltage (ov dd = min, i ol = 100 a) v ol ? 0.2 v
48 0926d?hirel?12/09 pc8610 [preliminary] e2v semiconductors sas 2009 3.14.2 gpio ac timing specifications table 3-41 provides the gpio input and output ac timing specifications. notes: 1. input specifications are measur ed from the 50% level of the signal to the 50% level of the rising edge of clkin. timings are measured at the pin. 2. gpio inputs and outputs are asynchronous to an y visible clock. gpio outputs should be synchronized before use by any external synchronous logic. gpio inputs are required to be valid for at least t piwid ns to ensure proper operation. 3. the minimum pulse width is a function of the mpx/ platform clock. the minimum pulse width must be greater than or equal to 4 times the mpx/platform clock period. figure 3-21 provides the ac test load for the gpio figure 3-21. gpio ac test load 3.15 serial peripher al interface (spi) this section describes the dc and ac electrical specifications for the spi interface of the pc8610. 3.15.1 spi dc electrical characteristics table 3-42 provides the spi dc electrical characteristics. note: 1. note that the symbol v in , in this case, represents the ov in symbol referenced in table 3-1 on page 14 and table 3-2 on page 15 . table 3-41. gpio input and output ac timing specifications (1) characteristic symbol (2) min unit notes gpio inputs: minimum pulse width t piwid 7.5 ns (3) gpio outputs: minimum pulse width t gtowid 12 ns output z 0 = 50 ov dd /2 r l = 50 table 3-42. duart dc electrical characteristics parameter symbol min max unit high-level input voltage v ih 2ov dd + 0.3 v low-level input voltage v il ? 0.3 0.8 v input current (v in (1) = 0v or v in = v dd ) i in ? 5 a high-level output voltage (ov dd = min, i oh = ? 100 a) v oh ov dd ? 0.2 ? v low-level output voltage (ov dd = min, i ol = 100 a) v ol ? 0.2 v
49 0926d?hirel?12/09 e2v semiconductors sas 2009 pc8610 [preliminary] 3.15.2 spi ac timing specifications table 3-43 provides the spi input and output ac timing specifications. notes: 1. output specifications are meas ured from the 50 percent level of the rising edge of clkin to the 50 per- cent level of the signal. timi ngs are measured at the pin. 2. the symbols for timing specifications follow the pattern of t (first two letters of functional block)(signal)(state) (refer- ence)(state) for inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. for example, t nikhox symbolizes the internal timing (ni) for the time spi clk clock reference (k) goes to the high state (h) until outputs (o) are invalid (x). figure 3-22 provides the ac test load for the spi. figure 3-22. spi ac test load figure 3-23 through figure 3-24 represent the ac timings from table 3-43 on page 49 . note that although the specifications generally reference the rising edge of the clock, these ac timing diagrams also apply when the falling edge is the active edge. figure 3-23 shows the spi timings in slave mode (external clock). figure 3-23. spi ac timing in slave mode (external clock) diagram note: the clock edge is selectable on spi. table 3-43. spi ac timing specifications (1) characteristic symbol (2) min max unit spi outputs valid: master mode (internal clock) delay t nikhov 1ns spi outputs hold: master mode (internal clock) delay t nikhox ? 0.2 ns spi outputs valid: slave mode (external clock) delay t nekhov 8 ns spi outputs hold: slave mode (external clock) delay t nekhox 2ns spi inputs: master mode (internal clock) input setup time t niivkh 4 ns spi inputs: master mode (internal clock) input hold time t niixkh 0 ns spi inputs: slave mode (external clock) input setup time t neivkh 4 ns spi inputs: slave mode (external clock) input hold time t neixkh 2 ns output z 0 = 50 ov dd /2 r l = 50 spiclk (input) t neixkh t neivkh t nekhox input signals: spimiso (see note) output signals spimosi (see note)
50 0926d?hirel?12/09 pc8610 [preliminary] e2v semiconductors sas 2009 figure 3-24 shows the spi timings in master mode (internal clock) figure 3-24. spi ac timing in master mode (internal clock) diagram note: the clock edge is selectable on spi. 3.16 pci interface this section describes the dc and ac electric al specifications for the pci bus interface. 3.16.1 pci dc electrical characteristics table 3-44 provides the dc electrical characteristics for the pci interface. notes: 1. ranges listed do not meet the full range of the dc specifications of the pci 2.2 local bus specifications. 2. note that the symbol v in , in this case, represents the ov in symbol referenced in table 3-1 on page 14 and table 3-2 on page 15 . spiclk (output) t niixkh t nikhox input signals: spimiso (see note) output signals: spimosi (see note) t niivkh table 3-44. pci dc electrical characteristics (1) parameter symbol min max unit high-level input voltage v ih 2ov dd + 0.3 v low-level input voltage v il ? 0.3 0.8 v input current (v in (2) = 0v or v in = v dd ) i in ? 5 a high-level output voltage (ov dd = min, i oh = ? 100 a) v oh ov dd ? 0.2 ? v low-level output voltage (ov dd = min, i ol = 100 a) v ol ? 0.2 v
51 0926d?hirel?12/09 e2v semiconductors sas 2009 pc8610 [preliminary] 3.16.2 pci ac electrical specifications this section describe s the general ac timi ng parameters of the pci bus. note that the sysclk signal is used as the pci input clock. table 3-45 provides the pci ac timing specifications at 66 mhz. notes: 1. note that the symbols used for timing specifications herein follow the pattern of t (first two letters of functional block)(signal)(state) (reference)(state) for inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. for example, t pcivkh symbolizes pci timing (pc) with respect to the time the input signals (i) reach the valid state (v) relative to the sysclk clock, t sys , reference (k) going to the high (h) state or setup time. also, t pcrhfv symbolizes pci timing (pc) with respect to the time hard reset (r) went high (h) relative to the frame signal (f) going to the valid (v) state. 2. see the timing measurement conditions in the pci 2.2 local bus specifications. 3. all pci signals are measured from ov dd /2 of the rising edge of pci_sync_in to 0.4 ov dd of the sig- nal in question for 3.3-v pci signaling levels. 4. for purposes of active/float timing measurements, th e hi-z or off state is defined to be when the total current delivered through the component pin is less than or equal to the leakage current specification. 5. input timings are measured at the pin. 6. the timing parameter t sys indicates the minimum and maximum clk cycle times for the various speci- fied frequencies. the system clock period must be kept within the minimum and maximum defined ranges. for values see section 4.1 ?system clocking? on page 70 . 7. the setup and hold time is with respect to the ri sing edge of hreset . 8. the timing parameter t pcrhfv is a minimum of 10 clocks rather than the minimum of 5 clocks in the pci 2.2 local bus specifications. 9. the reset assertion timing requirement for hreset is 100 s. 10. guaranteed by characterization 11. guaranteed by design. 12. the timing parameter t pckhov is a minimum of 1.5 ns and a maximu m of 7.4 ns rather than the minimum of 2 ns and a maximum of 6 ns in the pci 2.3 local bus specifications. 13. the timing parameter t pcivkh is a minimum of 3.7 ns rather than the minimum of 3 ns in the pci 2.3 local bus specifications. 14. the timing parameter t pcixkh is a minimum of 0.8 ns rather than the minimum of 0 ns in the pci 2.3 local bus specifications. table 3-45. pci ac timing specifications at 66 mhz parameter symbol (1) min max unit notes sysclk to output valid t pckhov 1.5 7.4 ns (2)(3)(12) sysclk to output high impedance t pckhoz ? 14 ns (2)(4)(11) input setup to sysclk t pcivkh 3.7 ? ns (2)(5)(10)(13) input hold from sysclk t pcixkh 0.8 ? ns (2)(5)(10)(14) req64 to hreset (9) setup time t pcrvrh 10 t sys ? clocks (6)(7)(11) hreset to req64 hold time t pcrhrx 0 50 ns (7)(11) hreset high to first frame assertion t pcrhfv 10 ? clocks (8)(11)
52 0926d?hirel?12/09 pc8610 [preliminary] e2v semiconductors sas 2009 figure 3-25 provides the ac test load for pci. figure 3-25. pci ac test load figure 3-26 shows the pci input ac timing conditions. figure 3-26. pci input ac timing measurement conditions figure 3-27 shows the pci output ac timing conditions. figure 3-27. pci output ac timing measurement condition 3.17 high-speed serial interfaces (hssi) the pc8610 features two serializer/deserializer (serdes) interfaces to be used for high-speed serial interconnect applications. the serdes1 interface is d edicated for pci express (x 1/x2/x4) data transfers. the serdes2 interface is dedicated for pci express (x1/x2/x4/x8) data transfers. this section describes the common portion of serdes dc electrical specifications, which is the dc requirement for serdes reference clocks. the serdes data lane?s transmitter and receiver reference cir- cuits are also shown. 3.17.1 signal terms definition the serdes utilizes differential signa ling to transfer data acro ss the serial link. this section defines terms used in the description and spec ification of differential signals. output z 0 = 50 ov dd /2 r l = 50 t pcivkh clk input t pcixkh clk output delay t pckhov high-impedance t pckhoz output
53 0926d?hirel?12/09 e2v semiconductors sas 2009 pc8610 [preliminary] figure 3-28 on page 54 shows how the signals are defined. for illustration purpose, only one serdes lane is used for description. the figure shows waveform for either a transmitter output (sd n _tx and sd n _tx ) or a receiver input (sd n _rx and sd n _rx ). each signal swings between a volts and b volts where a > b. using this waveform, the definitions are as follows. to simp lify illustration, the following definitions assume that the serdes transmitter and receiver operate in a fully symmetrical differential signaling environment. 1. single-ended swing the transmitter output signals and the receiver input signals sd n _tx, sd n _tx , sd n _rx, and sd n _rx each have a peak-to-peak swing of a ? b volts. this is also referred as each signal wire?s single-ended swing. 2. differential output voltage, v od (or differential output swing): the differential output voltage (or swing) of the transmitter, v od , is defined as the difference of the two complimentary output voltages: v sd n _tx ? v sd n _tx . the v od value can be either positive or negative. 3. differential input voltage, v id (or differential input swing): the differential input voltage (or swing) of the receiver, v id , is defined as the difference of the two complimentary input voltages: v sd n _rx ? v sd n _rx . the v id value can be either positive or negative. 4. differential peak voltage, v diffp the peak value of the differential transmitter output signal or the differential receiver input signal is defined as differential peak voltage, v diffp = |a ? b| volts. 5. differential peak-to-peak, v diffp-p since the differential output signal of the transmitter and the differential input signal of the receiver each range from a ? b to -(a ? b) volts, the peak-to-peak value of the differential transmitter output signal or the differential receiver input signal is defined as differential peak-to-peak voltage, v diffp-p = 2 * v diffp = 2 * |(a ? b)| volts, which is twice of differential swing in amplitude, or twice of the differ- ential peak. for example, the output differentia l peak-peak voltage can also be calculated as v tx- diffp-p = 2 * |v od |. 6. differential waveform the differential waveform is constructed by subtracting the inverting signal (sd n _tx , for example) from the noninverting signal (sd n _tx, for example) within a differential pair. there is only one signal trace curve in a differential waveform. the voltage represented in the differential waveform is not ref- erenced to ground. refer to figure 3-37 on page 60 as an example for differential waveform. 7. common mode voltage, v cm the common mode voltage is equal to one half of the sum of the voltages between each conductor of a balanced interchange circuit and ground . in this example, for serdes output, v cm_out = (v sd n _tx + v sd n _tx )/2 = (a + b)/2, which is the arithmetic mean of the two complimentary output voltages within a differential pair. in a system, the common mode voltage may often diffe r from one component?s output to the other?s input. sometimes, it may be even different between the receiver input and driver output circuits within the same component. it?s also referred as the dc offset in some occasion.
54 0926d?hirel?12/09 pc8610 [preliminary] e2v semiconductors sas 2009 figure 3-28. differential voltage definition s for transmitter or receiver to illustrate these definitions using real values, co nsider the case of a cml (current mode logic) trans- mitter that has a common mode voltage of 2.25 v and each of its outputs, td and td , has a swing that goes between 2.5 and 2.0 v. using these values, t he peak-to-peak voltage swing of each signal (td or td ) is 500 mv p-p, which is referred as the single-end ed swing for each signal. in this example, since the differential signaling environment is fully symme trical, the transmitter output?s differential swing (v od ) has the same amplitude as each signal?s single-ended swing. the differential output signal ranges between 500 mv and -500 mv, in other words, v od is 500 mv in one phase and ?500 mv in the other phase. the peak differential voltage (v diffp ) is 500 mv. the peak-to-peak differential voltage (v diffp-p ) is 1000 mv p-p. 3.17.2 serdes reference clocks the serdes reference clock inputs are applied to an internal pll whose output creates the clock used by the corresponding serdes lanes. the serdes reference clocks inputs are sd n _ref_clk and sd n _ref_clk for pci express. the following sections describe the serdes re ference clock requirements and some application information. 3.17.2.1 serdes reference clock receiver characteristics figure 3-29 on page 55 shows a receiver reference diagram of the serdes reference clocks. ? the supply voltage requirements for x n v dd are specified in table 3-1 and table 3-2 on page 15 . ? serdes reference clock receiver reference circuit structure ?the sd n _ref_clk and sd n _ref_clk are internally ac-coupled differential inputs as shown in figure 3-29 on page 55 . each differential clock input (sd n _ref_clk or sd n _ref_clk ) has a 50 termination to sgnd followed by on-chip ac-coupling. ? the external reference clock driver must be able to drive this termination. ? the serdes reference clock input can be either differential or single-ended. refer to the differential mode and single-ended mode description below for further detailed requirements. ? the maximum average current requirement that also determines the common mode voltage range ? when the serdes reference clock differential i nputs are dc coupled externally with the clock driver chip, the maximum average current allowed for each input pin is 8 ma. in this case, the exact common mode input voltage is not critical as long as it is within the range allowed by the maximum average current of 8 ma (refer to the following bullet for more detail), since the input is ac-coupled on-chip. v cm = (a + b) / 2 a volts b volts differential swing, v id or v od = a - b differential peak voltage, v diffp = ia - bi differential peak-peak voltage, v diffpp = 2*v diffp (not shown) sdn_tx or sdn_rx sdn_tx or sdn_rx
55 0926d?hirel?12/09 e2v semiconductors sas 2009 pc8610 [preliminary] ? this current limitation sets the maximum common mode input voltage to be less than 0.4 v (0.4 v/50 = 8 ma) while the minimum common mode input level is 0.1 v above sgnd. for example, a clock with a 50/50 duty cycle can be produced by a clock driver with output driven by its current source from 0 to 16 ma (0?0.8 v), such that each phase of the differential input has a single-ended swing from 0 v to 800 mv with the common mode voltage at 400 mv. ? if the device driving the sd n _ref_clk and sdn_ref_clk inputs cannot drive 50 to sgnd dc, or it exceeds the maximum input curr ent limitations, then it must be ac-coupled off-chip. ? the input amplitude requirement ? this requirement is described in detail in the following sections. figure 3-29. receiver of serdes reference clocks 3.17.2.2 dc level requirement for serdes reference clocks the dc level requirement for the pc8610 serdes reference clock inputs is different depending on the signaling mode used to connect the cl ock driver chip and serdes reference clock inputs as described below. ? differential mode ? the input amplitude of the differential clock must be between 400 and 1600 mv differential peak-peak (or between 200 and 800 mv differential peak). in other words, each signal wire of the differential pair must have a single-ended swing less than 800 mv and greater than 200 mv. this requirement is the same for both external dcor ac-coupled connection. ? for external dc-coupled connection, as described in section 3.17.2.1 ?serdes reference clock receiver characte ristics? on page 54 the maximum average current requirements sets the requirement for average voltage (common mode voltage) to be between 100 and 400 mv. figure 3-30 on page 56 shows the serdes reference clock input requirement for dc-coupled connection scheme. ? for external ac-coupled connection, there is no common mode voltage requirement for the clock driver. since the external ac-coupling capacitor blocks the dc level, the clock driver and the serdes reference clock receiver operate in different command mode voltages. the serdes reference clock receiver in this connection scheme has its common mode voltage set to sgnd. each signal wire of the differential inputs is allowed to swing below and above the command mode voltage (sgnd). figure 3-31 on page 56 shows the serdes reference clock input requirement for ac-coupled connection scheme. input amp 50 50 sdn_ref_clk sdn_ref_clk
56 0926d?hirel?12/09 pc8610 [preliminary] e2v semiconductors sas 2009 ? single-ended mode ? the reference clock can also be single-ended. the sd n _ref_clk input amplitude (single- ended swing) must be between 400 and 800 mv peak-peak (from v min to v max ) with sd n _ref_clk either left unconnected or tied to ground. ?the sd n _ref_clk input average voltage must be between 200 and 400 mv. figure 3-32 on page 56 shows the serdes reference clock input requirement for single-ended signaling mode. ? to meet the input amplitude requirement, the reference clock inputs might need to be dc- or ac-coupled externally. for the best noise performance, the reference of the clock could be dc- or ac-coupled into the unused phase (sd n _ref_clk ) through the same source impedance as the clock input (sd n _ref_clk) in use. figure 3-30. differential reference clock input dc requirements (external dc-coupled) figure 3-31. differential reference clock input dc requirements (external ac-coupled) figure 3-32. single-ended reference clock input dc requirements v max 800 mv v min > 0v 100 mv v cm 400 mv sdn_ref_clk sdn_ref_clk 200 mv input amplitude or differential peak 800 mv v max v cm + 400 mv v max > v cm - 400 mv v cm sdn_ref_clk sdn_ref_clk 200 mv input amplitude or differential peak 800 mv 0v sdn_ref_clk sdn_ref_clk 400 mv sdn_ref_clk input amplitude 800 mv
57 0926d?hirel?12/09 e2v semiconductors sas 2009 pc8610 [preliminary] 3.17.2.3 interfacing with other differential signaling levels ? with on-chip termination to sgnd, the differential reference clocks inputs are hcsl (high-speed current steering logic) compatible dc-coupled. ? many other low voltage differential type outputs like lvds (low voltage differential signaling) can be used but may need to be ac-coupled due to the limited common mode input range allowed (100 to 400 mv) for dc-coupled connection. ? lvpecl outputs can produce signal with too large amplitude and may need to be dc-biased at clock driver output first, then followed with series attenuation resistor to reduce the amplitude, in addition to ac-coupling. note: figure 3-33 to figure 3-36 on page 59 are for conceptual reference only. due to the fact that clock driver chip's internal structure, output impedance and te rmination requirements are different between various clock driver chip manufacturers, it is very possible th at the clock circuit reference designs provided by clock driver chip vendor are different from what is shown below. they might also vary from one vendor to the other. therefore, e2v can neither provide the optimal cl ock driver reference circuits nor guarantee the cor- rectness of the following clock driv er connection reference circuits . the system designer is recommended to contact the selected clock driver chip vendor for the optimal reference circuits with the pc8610 serdes reference clock receiver requirement provided in this document. figure 3-33 shows the serdes reference clock connection re ference circuits for hcsl type clock driver. it assumes that the dc levels of the clock driver chip is compatible with pc8610 serdes reference clock input?s dc requirement. figure 3-33. dc-coupled differential connection with hcsl clock driver (reference only) figure 3-34 shows the serdes reference clock connection reference circuits for lvds type clock driver. since lvds clock driver?s common mode voltage is higher than the pc8610 serdes reference clock input?s allowed range (100 to 400 mv), ac-coupled c onnection scheme must be used. it assumes the lvds output driver features 50 termination resistor. it also assumes that the lvds transmitter estab- lishes its own common mode level without relying on the receiver or other external component. 50 50 sd n _ref_clk sd n _ref_clk clock driver 100 differential pwb trace clock driver vendor dependent source termination resistor clk_out clk_out hcsl clk driver chip 33 33 total 50 . assume clock driver?s output impedance is about 16 . pc8610 clk_out serdes refer. clk receiver clock driver
58 0926d?hirel?12/09 pc8610 [preliminary] e2v semiconductors sas 2009 figure 3-34. ac-coupled differential connection with lvds clock driver (reference only) figure 3-35 shows the serdes re ference clock conn ection reference circuits for lvpecl type clock driver. since lvpecl driver?s dc levels (both common mode voltages and ou tput swing) are incompati- ble with pc8610 serdes reference clock input?s dc requirement, ac-coupling has to be used. figure 3- 35 assumes that the lvpecl clo ck driver?s output impedance is 50 . r1 is used to dc-bias the lvpecl outputs prior to ac-coupling. its value could be ranged from 140 to 240 depending on clock driver vendor?s requirement. r2 is used together with the serdes reference clock receiver?s 50 termi- nation resistor to attenuate the lvpecl output?s differential peak level such that it meets the pc8610 serdes reference clock?s differential input amplitude requirement (between 200 and 800 mv differential peak). for example, if the lvpecl output?s diff erential peak is 900 mv and the desired serdes refer- ence clock input amplitude is selected as 600 mv, the attenuation factor is 0.67, which requires r2 = 25 . please consult clock driver chip manufacturer to verify whether this connection scheme is compati- ble with a particular clock driver chip. figure 3-35. ac-coupled differential co nnection with lvpecl clock driver (reference only) sd n _ref_clk sd n _ref_clk clock driver 100 differential pwb trace clk_out clk_out lvds clk driver chip 10 nf 10 nf pc8610 serdes refer. clk receiver 50 50 clock driver sd n _ref_clk sd n _ref_clk clock driver 100 differential pwb trace serdes refer. clk receiver clock driver clk_out clk_out lvpecl clk driver chip r2 r2 pc8610 10 nf 10 nf clk_out clk_out r2 r2 r1 clock driver 50 50 r1
59 0926d?hirel?12/09 e2v semiconductors sas 2009 pc8610 [preliminary] figure 3-36 shows the serdes reference clock connection reference circuits for a single-ended clock driver. it assumes the dc levels of the clock driver are compatible with pc8610 serdes reference clock input?s dc requirement. figure 3-36. single-ended connection (reference only) 3.17.2.4 ac requirements for serdes reference clocks the clock driver selected should provide a high qua lity reference clock with low phase noise and cycle- to-cycle jitter. phase noise less than 100 khz can be tracked by the pll and data recovery loops and is less of a problem. phase noise above 15 mhz is filtered by the pll. the most problematic phase noise occurs in the 1-15 mhz range. the source impedance of the clock driver should be 50 to match the transmission line and reduce reflections which are a source of noise to the system. table 3-46 describes some ac parameters common to pci express protocols. notes: 1. measurement taken from single ended waveform. 2. measurement taken from differential waveform. 3. measured from ?200 to +200 mv on the differential waveform (derived from sd n _ref_clk minus sd n _ref_clk ). the signal must be monotonic through the measurement region for ri se and fall time. the 400 mv measurement window is cen- tered on the differential zero crossing. see figure 3-37 on page 60 . 4. matching applies to rising edge rate for sd n _ref_clk and falling edge rate for sd n _ref_clk . it is measured using a 200 mv window centered on the median cross point where sd n _ref_clk rising meets sd n _ref_clk falling. the median cross point is used to calculate the voltage thresholds the osci lloscope is to use for the edge rate calculations. the rise edg e rate of sd n _ref_clk should be compared to the fall edge rate of sd n _ref_clk , the maximum allowed difference should not exceed 20% of the slowest edge rate. see figure 3-38 on page 60 . sd n _ref_clk sd n _ref_clk 100 differential pwb trace clock driver clk_out single-ended clk driver chip pc8610 33 total 50 . assume clock driver?s output impedance is about 16 . 50 serdes refer. clk receiver 50 50 table 3-46. serdes reference clock common ac parameters (at recommended operatin g conditions with x1v dd or x2v dd = 1.0 v 5% and 1.025 v 5%) parameter symbol min max unit notes rising edge rate rise edge rate 1.0 4.0 v/ns (2)(3) falling edge rate fall edge rate 1.0 4.0 v/ns (2)(3) differential input high voltage v ih +200 mv (2) differential input low voltage v il ??200mv (2) rising edge rate (sd n _ref_clk) to falling edge rate (sd n _ref_clk ) matching rise-fall matching ? 20 % (1)(4)
60 0926d?hirel?12/09 pc8610 [preliminary] e2v semiconductors sas 2009 figure 3-37. differential measurement po ints for rise and fall time figure 3-38. single-ended measurement points for rise and fall time matching the other detailed ac requirements of the serdes re ference clocks is defined by each interface protocol based on application usage. refer to the following sections for detailed information: ? section 3.18.2 ?ac requirements for pci express serdes clocks? on page 61 . 3.17.3 serdes transmitter and receiver reference circuits figure 3-39 shows the reference circuits for serdes data lane?s transmitter and receiver. figure 3-39. serdes transmitter and re ceiver reference circuits the dc and ac specification of serdes data lanes are defined in each interface protocol section below (pci express) in this document based on the application usage:? ? section 3.18 ?pci express? on page 61 note that external ac coupling capacitor is require d for the above serial transmission protocols with the capacitor value defined in specification of each protocol section. v il = -200 mv 0.0 v sd n _ref_clk minus sd n _ref_clk rise edge rate fall edge rate v ih = +200 mv sdn_ref_clk sdn_ref_clk sdn_ref_clk sdn_ref_clk 50 50 receiver transmitter sd1_tx n or sd2_tx n sd1_tx n or sd2_tx n sd1_rx n or sd2_rx n sd1_rx n or sd2_rx n 50 50
61 0926d?hirel?12/09 e2v semiconductors sas 2009 pc8610 [preliminary] 3.18 pci express this section describes the dc and ac electrical s pecifications for the pci express bus of the pc8610. 3.18.1 dc requirements for pci express sd n _ref_clk and sd n _ref_clk for more information, see section 3.17.2 ?serdes reference clocks? on page 54 . 3.18.2 ac requirements for pci express serdes clocks table 3-47 lists ac requirements. 3.18.3 clocking dependencies the ports on the two ends of a link must transmit data at a rate that is within 60 0 parts per million (ppm) of each other at all times. this is specified to allow bit rate clock sources with a 300 ppm tolerance. 3.18.4 physical layer specifications the following is a summary of the specifications for the physical layer of pci express on this device. for further details as well as the specifications of t he transport and data link layer please use the pci express base specification. rev. 1.0a document. 3.18.4.1 differential tr ansmitter (tx) output table 3-48 defines the specifications for the differential output at all transmitters (txs). the parameters are specified at the component pins. table 3-47. sd n _ref_clk and sd n _ref_clk ac requirements symbol parameter description min typical max units t ref refclk cycle time ? 10 ? ns t refcj refclk cycle-to-cycle jitter. difference in the period of any two adjacent refclk cycles 100 ps t refpj phase jitter. deviation in edge location with respect to mean edge location -50 ? 50 ps table 3-48. differential transmitter (t x) output specifications symbol parameter min nom max units comments ui unit interval 399.88 400 400.12 ps each ui is 400 ps 300 ppm. ui does not account for spread spectrum clock dictated variations. see note (1) . v tx-diffp-p differential peak-to- peak output voltage 0.8 1.2 v v tx-diffp-p = 2*|v tx-d+ - v tx-d- |. see note (2) . v tx-de-ratio de- emphasized differential output voltage (ratio) ?3.0 ?3.5 ?4.0 db ratio of the v tx-diffp-p of the second and following bits after a transition divided by the v tx-diffp-p of the first bit after a transition. see note (2) . t tx-eye minimum tx eye width 0.70 ui the maximum transmitter jitter can be derived as t tx-max-jitter = 1 ? ttx-eye= 0.3 ui. see notes (2) and (3) . t tx-eye-median-to-max- jitter maximum time between the jitter median and maximum deviation from the median. 0.15 ui jitter is defined as the meas urement variation of the crossing points (v tx-diffp-p = 0v) in relation to a recovered tx ui. a recovered tx ui is calculated over 3500 consecutive unit intervals of sample data. jitter is measured using all edges of the 250 consecutive ui in the center of the 3500 ui used for calculating the tx ui. see notes (2) and (3) .
62 0926d?hirel?12/09 pc8610 [preliminary] e2v semiconductors sas 2009 t tx-rise , t tx-fall d+/d- tx output rise/fall time 0.125 ui see notes (2) and (5) v tx-cm-acp rms ac peak common mode output voltage 20 mv v tx-cm-acp = rms(|v txd+ ? v txd- |/2 ? v tx-cm-dc ) v tx-cm-dc = dc (avg) of |v tx-d+ ? v tx-d- |/2 see note (2) v tx-cm-dc-active-idle- delta absolute delta of dc common mode voltage during lo and electrical idle 0 100 mv |v tx-cm-dc (during lo) ? v tx-cm-idle-dc (during electrical idle) |<=100 mv v tx-cm-dc = dc (avg) of |v tx-d+ ? v tx-d- |/2 [lo] v tx-cm-idle-dc = dc (avg) of |v tx-d+ ? v tx-d- |/2 [electrical idle] see note (2) . v tx-cm-dc-line-delta absolute delta of dc common mode between d+ and d? 025mv |v tx-cm-dc-d+ ? v tx-cm-dc-d- | <= 25 mv v tx-cm-dc-d+ = dc (avg) of |v tx-d+ | v tx-cm-dc-d- = dc (avg) of |v tx-d- | see note (2) . v tx-idle-diffp electrical idle differential peak output voltage 020mv v tx-idle-diffp = iv tx-idle-d+ ? v tx-idle-d- | <= 20 mv. see note (2) . v tx-rcv-detect the amount of voltage change allowed during receiver detection 600 mv the total amount of voltage change that a transmitter can apply to sense whether a low impedance receiver is present. see note (6) . v tx-dc-cm the tx dc common mode voltage 03.6 v the allowed dc common mode voltage under any conditions. see note (6) . i tx-short tx short circuit current limit 90 ma the total current the transmitter can provide when shorted to its ground t tx-idle-min minimum time spent in electrical idle 50 ui minimum time a transmitter must be in electrical idle utilized by the receiver to start looking for an electrical idle exit after successfully receiving an electrical idle ordered set t tx-idle-set-to-idle maximum time to transition to a valid electrical idle after sending an electrical idle ordered set 20 ui after sending an electrical idle ordered set, the transmitter must meet all elec trical idle specifications within this time. this is considered a debounce time for the transmitter to meet electr ical idle after transitioning from lo. t tx-idle-to-diff-data maximum time to transition to valid tx specifications after leaving an electrical idle condition 20 ui maximum time to meet all tx specifications when transitioning from electrical idle to sending differential data. this is considered a debounce time for the tx to meet all tx specifications a fter leaving electrical idle rl tx-diff differential return loss 12 db measured over 50 mhz to 1.25 ghz. see note (4) rl tx-cm common mode return loss 6 db measured over 50 mhz to 1.25 ghz. see note (4) z tx-diff-dc dc differential tx impedance 80 100 120 tx dc differential mode low impedance z tx-dc transmitter dc impedance 40 required tx d+ as wellall states table 3-48. differential transmitter (tx) outp ut specifications (continued) symbol parameter min nom max units comments
63 0926d?hirel?12/09 e2v semiconductors sas 2009 pc8610 [preliminary] notes: 1. no test load is necessarily associated with this value. 2. specified at the measurement point into a timi ng and voltage compliance test load as shown in figure 3-42 on page 67 and measured over any 250 consecutive tx uis. (also re fer to the transmitter compliance eye diagram shown in figure 3-40 on page 64 ) 3. a t tx-eye = 0.70 ui provides for a total sum of dete rministic and random jitter budget of t tx-jitter-max = 0.30 ui for the trans- mitter collected over any 250 consecutive tx uis. the t tx-eye-median-to-max-jitter median is less than half of the total tx jitter budget collected over any 250 consecutive tx uis. it should be noted t hat the median is not the sa me as the mean. the jitter median describes the point in time where th e number of jitter points on either side is approximately equal as opposed to the averaged time value. 4. the transmitter input impedance shall result in a differential return loss greater than or equal to 12 db and a common mode return loss greater than or equal to 6 db over a frequency range of 50 mhz to 1.25 ghz. th is input impedance requirement applies to all valid input levels. the referenc e impedance for return loss measurements is 50 to ground for both the d+ and d- line (that is, as measured by a vector network analyzer with 50 probes: see figure 3-42 on page 67 ). note that the series capacitors c tx is optional for the return loss measurement. 5. measured between 20-80% at transmitter package pins into a test load as shown in figure 3-42 for both v tx-d+ and v tx-d- . 6. see section 4.3.1.8 of the pci ex press base specifications rev 1.0a 7. see section 4.2.6.3 of the pci ex press base specifications rev 1.0a 3.18.4.2 transmitter compliance eye diagrams the tx eye diagram in figure 3-40 on page 64 is specified using the passive compliance/test measure- ment load (see figure 3-42 ) in place of any real pci express interconnect + rx component. there are two eye diagrams that must be met for the transmitter. both eye diagrams must be aligned in time using the jitter median to locate the center of the eye diagram. the different eye diagrams will differ in voltage depending whether it is a transition bit or a de-emphasized bit. the exact reduced voltage level of the de-emphasized bit will always be relative to the transition bit. the eye diagram must be valid for any 250 consecutive uis. a recovered tx ui is calculated over 3500 consecutive unit intervals of sample data. the eye diagram is created using all edges of the 250 consecutive ui in the center of the 3500 ui used for calculating the tx ui. note: it is recommended that the recovered tx ui is ca lculated using all edges in the 3500 consecutive ui inter- val with a fit algorithm using a minimization merit function (i.e., least squares and median deviation fits). l tx-skew lane-to-lane output skew 500 + 2 ui ps static skew between any two transmitter lanes within a single link c tx ac coupling capacitor 75 200 nf all transmitters shall be ac coupled. the ac coupling is required either within the m edia or within the transmitting component itself. t crosslink crosslink random timeout 01 ms this random timeout helps reso lve conflicts in crosslink configuration by eventually resulting in only one downstream and one upstream port. see note (7) . table 3-48. differential transmitter (tx) outp ut specifications (continued) symbol parameter min nom max units comments
64 0926d?hirel?12/09 pc8610 [preliminary] e2v semiconductors sas 2009 figure 3-40. minimum transmitter timing and voltage output compliance specifications 3.18.4.3 differential receiver (rx) input specifications table 3-49 defines the specifications for the differential input at all receivers (rxs). the parameters are specified at the component pins. v tx-diff = 0 mv (d+ d- crossing point) v tx-diff = 0 mv (d+ d- crossing point) (transition bit) v tx-diffp-p-min = 800 mv (de-emphasized bit) 566 mv (3 db) >= v tx-diffp-p-min >= 505 mv (4 db) .07 ui = ui - 0.3 ui(j tx-total-max ) (transition bit) v tx-diffp-p-min = 800 mv table 3-49. differential receiver (r x) input specifications symbol parameter min nom max units comments ui unit interval 399.88 400 400.12 ps each ui is 400 ps 300 ppm. ui does not account for spread spectrum clock dictated variations. see note (1) . v rx-diffp-p differential peak-to-peak output voltage 0.175 1.200 v v rx-diffp-p = 2*|v rx-d + ? v rx-d- |. see note (2) . t rx-eye minimum receiver eye width 0.4 ui the maximum interconnect media and transmitter jitter that can be tolerated by the receiver can be derived as t rx-max-jitter = 1 ? t rx-eye = 0.6 ui. see notes (2) and (3) . t rx-eye-median-to-max -jitter maximum time between the jitter median and maximum deviation from the median. 0.3 ui jitter is defined as the measurement variation of the crossing points (v rx-diffp-p = 0v) in relation to a recovered tx ui. a recovered tx ui is calculated over 3500 consecutive unit intervals of sample data. jitter is measured using all edges of the 250 consecutive ui in the center of the 3500 ui used for calculating the tx ui. see notes (2) , (3) and (7) . v rx-cm-acp ac peak common mode input voltage 150 mv v rx-cm-acp = |v rxd+ ? v rxd- |/2 ? v rx-cm-dc v rx-cm-dc = dc (avg) of |v rx-d+ ? v rx-d- |/2 see note (2)
65 0926d?hirel?12/09 e2v semiconductors sas 2009 pc8610 [preliminary] notes: 1. no test load is necessarily associated with this value. 2. specified at the measurement poi nt and measured over any 250 c onsecutive uis. the test load in figure 3-42 on page 67 should be used as the rx device when taking measurements (a lso refer to the receiver compliance eye diagram shown in figure 3-41 on page 66 ). if the clocks to the rx and tx are not derived fr om the same reference clock, the tx ui recovered from 3500 consecutive ui must be used as a reference for the eye diagram. 3. a t rx-eye = 0.40 ui provides for a total sum of 0.60 ui determinis tic and random jitter budget for the transmitter and inter- connect collected any 250 consecutive uis. the t rx-eye-median-to-max-jitter specification ensures a jit ter distribution in which the median and the maximum deviation from the median is less than half of the total. ui jitter budget collected over any 250 consecutive tx uis. it should be noted that the median is not the same as the mean. the jitter median describes the point in time where the number of jitter points on either side is approximately equal as opposed to the averaged time value. if the clocks to the rx and tx are not derived from the same referenc e clock, the tx ui recovered from 3500 consecutive ui must be used as the reference for the eye diagram. 4. the receiver input impedance shall result in a differential re turn loss greater than or equal to 15 db with the d+ line biase d to 300 mv and the d- line biased to ?300 mv and a common mode return loss greater than or equal to 6 db (no bias required) over a frequency range of 50 mhz to 1.25 ghz. this input impedance requ irement applies to all valid input levels. the reference impedance for return loss measurements for is 50 to ground for both the d+ and d- line (that is, as mea- sured by a vector network analyzer with 50 probes ? see figure 3-42 ). note: that the se ries capacitors c tx is optional for the return loss measurement. 5. impedance during all ltssm states. when transitioning from a fundamental reset to detect (t he initial state of the ltssm) there is a 5 ms transition time before receiver terminatio n values must be met on all un-configured lanes of a port. 6. the rx dc common mode impedance that exists when no power is present or fundamental re set is asserted. this helps ensure that the receiver detect circuit will not falsely assume a receiver is powered on when it is not. this term must be measured at 300 mv above the rx ground. 7. it is recommended that the recovered tx ui is calculated using all edges in the 3500 consecutive ui interval with a fit algo- rithm using a minimization merit function. least squares and me dian deviation fits have worked well with experimental and simulated data. rl rx-diff differential return loss 15 db measured over 50 mhz to 1.25 ghz with the d+ and d-lines biased at +300 mv and ?300 mv, respectively. see note (4) rl rx-cm common mode return loss 6db measured over 50 mhz to 1.25 ghz with the d+ and d-lines biased at 0v. see note (4) z rx-diff-dc dc differential input impedance 80 100 120 rx dc differential mode impedance. see note (5) z rx-dc dc input impedance 40 50 60 required rx d+ as well as d-dc impedance (50 20% tolerance). see notes (2) and (5) . z rx-high-imp-dc powered down dc input impedance 200 k required rx d+ as we ll as d-dc impedance when the receiver terminations do not have power. see note (6) . v rx-idle-det-diffp-p electrical idle detect threshold 65 175 mv v rx-idle-det-diffp-p = 2*|v rx-d+ ? v rx-d- | measured at the package pins of the receiver t rx-idle-det-diff-entertime unexpected electrical idle enter detect threshold integration time 10 ms an unexpected electrical idle (v rx-diffp-p < v rx-idle- det-diffp-p ) must be recognized no longer than t rx- idle-det-diff-entering to signal an unexpected idle condition. l tx-skew total skew 20 ns skew across all lanes on a link. this includes variation in the length of skp ordered set (e.g. com and one to five symbols) at the rx as well as any delay differences arising from the interconnect itself. table 3-49. differential receiver (rx) input specifications (continued) symbol parameter min nom max units comments
66 0926d?hirel?12/09 pc8610 [preliminary] e2v semiconductors sas 2009 3.18.5 receiver compliance eye diagrams the rx eye diagram in figure 3-41 on page 66 is specified using the passive compliance/test measure- ment load (see figure 3-42 on page 67 ) in place of any real pci express rx component. note: in general, the minimum receiver eye diagram measured with the compliance/test measurement load (see figure 3-42 ) will be larger than the minimum receiver eye diagram measured over a range of systems at the input receiver of any real pci ex press component. the degra ded eye diagram at the input receiver is due to traces internal to the pack age as well as silicon paras itic characteristics which cause the real pci express component to vary in impedance from the compliance/test measurement load. the input receiver eye diagram is implement ation specific and is not specified. rx component designer should provide additional margin to adequately compensate for the degraded minimum receiver eye diagram (shown in figure 3-41 on page 66 ) expected at the input receiver based on some adequate combination of system si mulations and the retu rn loss measured look ing into the rx pack- age and silicon. the rx eye diagram must be aligned in time using the jitter median to locate the center of the eye diagram. the eye diagram must be valid for any 250 consecutive uis. a recovered tx ui is calculated over 3500 consecutive unit intervals of sample data. the eye diagram is created using all edges of the 250 consecutive ui in the center of the 3500 ui used for calculating the tx ui. note: the reference impedance for return loss measurements is 50 to ground for both the d+ and d- line (i.e., as measured by a vector network analyzer with 50 probes ; see figure 3-42 on page 67 ). note that the series capacitors, c tx , are optional for the return loss measurement. figure 3-41. minimum receiver eye timing and voltage compliance specification 3.18.5.1 compliance test and measurement load the ac timing and voltage parameters must be verifi ed at the measurement point, as specified within 0.2 inches of the package pins, into a test/measurement load shown in figure 3-42 . note: the allowance of the measurement point to be within 0.2 inches of the package pins is meant to acknowl- edge that package/board routing may benefit from d+ and d- not being exactly matched in length at the package pin boundary. v rx-diff = 0 mv (d+ d- crossing point) v rx-diff = 0 mv (d+ d- crossing point) 0.4 ui = t rx-eye-min v rx-diffp-p- min > 175 mv
67 0926d?hirel?12/09 e2v semiconductors sas 2009 pc8610 [preliminary] figure 3-42. compliance test/measurement load 3.19 jtag this section describes the dc and ac electrical spec ifications for the ieee 1149.1 (jtag) interface of the pc8610. 3.19.1 jtag dc electrical characteristics table 3-50 provides the jtag dc electrical characteristics for the jtag interface. note: 1. note that the symbol v in , in this case, represents the ov in symbol referenced in table 3-1 on page 14 and table 3-2 on page 15 . 3.19.2 jtag ac electrical specifications table 3-51 provides the jtag ac timing specifications as defined in figure 3-44 on page 69 through figure 3-46 on page 69 . d+ package pin d- package pin tx silicon + package r = 50 r = 50 c = c tx c = c tx table 3-50. jtag dc electrical characteristics parameter symbol min max unit high-level input voltage v ih 2ov dd + 0.3 v low-level input voltage v il ?0.3 0.8 v input current ( v in (1) = 0v or v in = v dd ) i in ? 5 a high-level output voltage ( ov dd = min, i oh = ?100 a) v oh ov dd ? 0.2 ? v low-level output voltage ( ov dd = min, i ol = 100 a) v ol ? 0.2 v table 3-51. jtag ac timing specificatio ns (independent of sysclk) (1) (at recommended operating conditions, see table 3-2 on page 15 ) parameter symbol (2) min max unit notes jtag external clock frequency of operation f jtg 0 33.3 mhz jtag external clock cycle time t jtg 30 ? ns jtag external clock pulse width measured at 1.4v t jtkhkl 15 ? ns jtag external clock rise and fall times t jtgr & t jtgf 02ns (6) trst assert time t trst 25 ? ns (3)
68 0926d?hirel?12/09 pc8610 [preliminary] e2v semiconductors sas 2009 notes: 1. all outputs are measured from the midp oint voltage of the falling/rising edge of t tclk to the midpoint of the signal in question. the output timings are measured at the pins. al l output timings assume a purely resistive 50 load (see figure 3-14 on page 40 ). time-of-flight delays must be added for tr ace lengths, vias, and connectors in the system. 2. the symbols used for timing specifications herein follow the pattern of t (first two letters of functional bl ock)(signal)(state) (reference)(state) for inputs and t (first two letters of functional bl ock)(reference)(state)(signal)(state) for outputs. for example, t jtdvkh symbolizes jtag device timing (jt) with respect to the time data input signals (d ) reaching the valid state (v) relative to the t jtg clock reference (k) going to the high (h) state or setup time. also, t jtdxkh symbolizes jtag timing (jt) with respect to the time data input signals (d) went invalid (x) relative to the t jtg clock reference (k) going to the high (h) state. note that, in general, the clock reference symbol representation is based on three letters representing the clock of a particular functional. for rise and fall times, the latter convention is used with the appropriate letter: r (rise) or f (fall). 3. trst is an asynchronous level sensitive signal. the setup time is for test purposes only. 4. non-jtag signal input timing with respect to t tclk . 5. non-jtag signal output timing with respect to t tclk . 6. guaranteed by design. figure 3-43 provides the ac test load for tdo and the boundary-scan outputs. figure 3-43. ac test load for the jtag interface input setup times: boundary-scan data tms, tdi t jtdvkh t jtivkh 4 0 ? ? ns (4) input hold times: boundary-scan data tms, tdi t jtdxkh t jtixkh 20 25 ? ? ns (4) valid times: boundary-scan data tdo t jtkldv t jtklov 4 4 20 25 ns (5) output hold times: boundary-scan data tdo t jtkldx t jtklox 30 30 ? ? ns (5) jtag external clock to output high impedance: boundary-scan data tdo t jtkldz t jtkloz 3 3 19 9 ns (5)(6) table 3-51. jtag ac timing specificatio ns (independent of sysclk) (1) (at recommended operating conditions, see table 3-2 on page 15 ) (continued) parameter symbol (2) min max unit notes ov dd /2 output z 0 = 50 r l = 50
69 0926d?hirel?12/09 e2v semiconductors sas 2009 pc8610 [preliminary] figure 3-44 provides the jtag clock input timing diagram. figure 3-44. jtag clock input timing diagram note: vm = midpoint voltage (ov dd /2) figure 3-45 provides the trst timing diagram. figure 3-45. trst timing diagram note: vm = midpoint voltage (ov dd /2) figure 3-46 provides the boundary-scan timing diagram. figure 3-46. boundary-scan timing diagram note: vm = midpoint voltage (ov dd /2) vm vm vm t jtg t jtgr t jtgf t jtkhkl jtag external clock trst t trst vm vm vm jtag external clock boundary data inputs boundary data outputs boundary data outputs t jtdxkh t jtdvkh t jtkldv t jtkldz output data valid t jtkldx vm input data valid output data valid
70 0926d?hirel?12/09 pc8610 [preliminary] e2v semiconductors sas 2009 4. hardware design considerations this section provides electrical and thermal design recommendations fo r successful application of the pc8610. 4.1 system clocking this section describes the pll configuration of the pc8610. note that the platform clock is identical to the internal mpx bus clock. this device includes six plls, as follows: 1. the platform pll generates th e platform clock from the exte rnally supplied sysclk input. the frequency ratio between the platform and sysclk is selected using the platform pll ratio con- figuration bits as described in section 4.1.2 ?platform/mpx to sysclk pll ratio? on page 71 . 2. the e600 core pll generates the core clock from the platform clock. the frequency ratio between the e600 core clock and the platform clock is selected using the e600 pll ratio config- uration bits as described in section 4.1.3 ?e600 core to mpx/platform clock pll ratio? on page 72 . 3. the pci pll generates the clocking for the pci bus 4. each of the two serdes blocks has a pll. 4.1.1 clock ranges table 4-1 provides the clocking specifications for the processor core. notes: 1. caution: the mpx clock to sysclk ratio and e600 core to mpx clock ratio settings must be chosen such that the resulting sysclk frequency, e600 (core) frequency, and mpx clock freq uency do not exceed their respective maximum or minimum operating frequencies. refer to section 4.1.2 ?platform/mpx to sysclk pll ratio? on page 71 and section 4.1.3 ?e600 core to mpx/platform clock pll ratio? on page 72 , for ratio settings. 2. the minimum e600 core frequency is based on the minimum platform clock frequency of 333 mhz. 3. the reset config pin cfg_core_s peed must be pulled low if the core frequency is 800 mhz or below. table 4-2 provides the clocking specifications for the memory bus. notes: 1. caution: the mpx clock to sysclk ratio and e600 core to m px clock ratio settings must be chosen such that the resulting sysclk frequency, e600 (core) frequency, and mpx clock frequency do not exceed their respec- tive maximum or minimum operating frequencies. refer to section 4.1.2 ?platform/mpx to sysclk pll ratio? on page 71 . 2. the memory bus clock speed is half the ddr/ddr2 data rate, hence, half the mpx clock frequency. table 4-1. processor core clocking specifications characteristic maximum processor core frequency unit notes 800 mhz 1066 mhz 1333 mhz min max min max min max e600 core processor frequency 666 800 666 1066 666 1333 mhz (1)(2)(3) table 4-2. memory bus clocking specifications characteristic maximum processor core frequency unit notes 800, 1066, 1333 mhz min max memory bus clock frequency 166 266 mhz (1)(2)
71 0926d?hirel?12/09 e2v semiconductors sas 2009 pc8610 [preliminary] table 4-3 provides the clocking spec ifications for the local bus. note: 1. the local bus clock speed on lclk[0:2] is determined by mpx clock divided by the local bus ratio pro- grammed in lcrr[clkdiv]. see the reference manual for the pc8610 for more information. table 4-4 provides the clocking specifications for the platform/mpx bus. note: 1. caution : the mpx clock to sysclk ratio and e600 core to mpx clock ratio settings must be chosen such that the resulting sysclk frequency, e600 (core) frequency, and mpx clock frequency do not exceed their respective maximum or minimum operating frequencies. refer to section 4.1.2 ?plat- form/mpx to sysclk pll ratio? on page 71 . 4.1.2 platform/mpx to sysclk pll ratio the clock that drives the internal mpx bus is called the platform clock. the frequency of the platform clock is set using the following reset signals, as shown in table 4-5 : ? sysclk input signal ? binary value on diu_ld[10], la[28:31] (cfg_sys_pll[0:4] ? reset config) at power up note that there is no default for this pll ratio; th ese signals must be pulled to the desired values. also note that the ddr data rate is the determining factor in selecting the platform frequency, since the plat- form frequency must equal the ddr data rate. for specifications on the pci_clk, refer to the pci 2.2 specification. table 4-3. local bus clocking specifications characteristic maximum processor core frequency unit notes 800, 1066, 1333 mhz min max local bus clock frequency 22 133 mhz (1) table 4-4. platform/mpx bus clock ing specifications characteristic maximum processor core frequency unit notes 800, 1066, 1333 mhz min max platform/mpx bus clock speed 333 533 mhz (1) table 4-5. platform/sysclk clock ratios binary value of diu_ld[10], la[28:31] signals platform:sysclk ratio binary value of diu_ld[10], la[28:31] signals platform:sysclk ratio 00010 2:1 01010 10:1 00011 3:1 01100 12:1 00100 4:1 01110 14:1 00101 5:1 01111 15:1 00110 6:1 10000 16:1 00111 7:1 10001 17:1 01000 8:1 10010 18:1 01001 9:1 all others reserved
72 0926d?hirel?12/09 pc8610 [preliminary] e2v semiconductors sas 2009 4.1.3 e600 core to mpx/platform clock pll ratio the clock ratio between the e600 core and the platfo rm clock is determined by the binary value of lbctl, lale, lgpl0/loe /lfre , diu_ld4 (cfg_core_pll[0:3] ? reset config) signals at power up. table 4-6 describes the supported ratios. 4.1.4 frequency options 4.1.4.1 sysclk and platform frequency options table 4-7 shows the expected frequency options for sysclk and platform frequencies. note: 1. platform/mpx frequency values are shown rounded down to the nearest whole number (decimal place accuracy removed) table 4-6. e600 core/platform clock ratios binary value of lbctl, lale, lgpl0/loe /lfre , diu_ld4 signals e600 core : mpx/platform ratio 1000 2:1 1010 2.5:1 1100 3:1 1110 3.5:1 0000 4:1 0010 4.5:1 all others reserved table 4-7. sysclk and platform frequency options platform: sysclk ratio sysclk (mhz) 33.33 66.66 83.33 100.00 111.11 133.33 platform/mpx frequency (mhz) (1) 3:1 333 400 4:1 333 400 533 5:1 333 500 6:1 400 500 8:1 533 9:1 10:1 333 12:1 400 16:1 533
73 0926d?hirel?12/09 e2v semiconductors sas 2009 pc8610 [preliminary] 4.2 power supply d esign and sequencing 4.2.1 pll power supply filtering each of the plls listed above is provided with power through independent power supply pins (av dd _plat, av dd _core, av dd _pci, and sd n av dd respectively). the av dd level should always be equivalent to v dd , and preferably these voltages will be derived directly from v dd through a low fre- quency filter scheme such as the following. there are a number of ways to reliably provide power to the plls, but the recommended solution is to provide in dependent filter circuits per pll power supply, one to each of the av dd type pins. by providing independent filter s to each pll the opportunity to cause noise injection from one pll to the other is reduced. this circuit is intended to filter noise in the pl ls resonant frequency range from a 500 khz to 10 mhz range. it should be built with surface mount capacit ors with minimum effective series inductance (esl). consistent with the recommendations of dr. howard johnson in high speed digital design: a handbook of black magic (prentice hall, 1993), multiple sm all capacitors of equal value are recommended over a single large value capacitor. each circuit should be pl aced as close as possibl e to the specific av dd type pin being supplied to mini- mize noise coupled from nearby circuits. it should be possible to route directly from the capacitors to the av dd type pin, which is on the periphery of 783 fc-p bga the footprint, without the inductance of vias. figure 4-1 shows the filter circuit for the platform pll power supplies (av dd _plat). figure 4-1. pc8610 pll power supply filter circuit (for platform) figure 4-1 shows the filter circuit for the core pll power supply (av dd _core). figure 4-2. pc8610 pll power supply filter circuit (for core) the sd n av dd signals provide power for the analog portions of the serdes plls. to ensure stability of the internal clock, the power supplied to the pll is filtered using a circuit similar to the one shown in fig- ure 4-3 . for maximum effectiveness, the filter circui t is placed as closely as possible to the sd n av dd balls to ensure it filters out as much noise as possible. the ground connec tion should be near the sd n av dd balls. the 0.003-f capacitor is closest to the balls, followed by the 1-f capacitor, and finally the 1 resistor to the board supply plane. the capacitors are connected from sd n av dd to the ground plane. use ceramic chip capacitors with the highes t possible self-resonant frequency. all traces should be kept short, wide and direct. 2.2 f 2.2 f gnd low esl surface mount capacitors 10 av dd _plat v dd _plat v dd _core av dd _core 2.2 f 2.2 f gnd low esl surface mount capacitors 10
74 0926d?hirel?12/09 pc8610 [preliminary] e2v semiconductors sas 2009 figure 4-3. serdes pll power supply filter note: 1. an 0805 sized capacitor is reco mmended for system initial bring-up. note the following: ?sd n av dd should be a filtered version of sv dd . ? signals on the serdes interface are fed from the sv dd power plane. 4.3 decoupling recommendations due to large address and data buses, and high operati ng frequencies, the device can generate transient power surges and high frequency noise in its power supply, especially while driving large capacitive loads. this noise must be prevented from reaching other components in the pc8610 system, and the device itself requires a clean, tightly regulated source of power. therefore, it is recommended that the system designer place at least one decoupling capacitor at each v dd , bv dd , ov dd , gv dd , v dd _core, and v dd _plat pin of the device. these decoupling capaci tors should receive their power from separate v dd , bv dd , ov dd , gv dd , v dd _core, v dd _plat and gnd power planes in the pcb, utilizi ng short traces to minimize inductance. capacitors may be placed directly under the device using a standard escape pattern. others may surround the part. these capacitors should have a value of 0.01 or 0.1 f. only ceramic smt (surface mount technol ogy) capacitors should be used to minimize lead inductance, pref- erably 0402 or 0603 sizes. in addition, it is recommended that there should be several bulk storage capacitors distributed around the pcb, feeding the v dd , bv dd , ov dd , gv dd , v dd _core, and v dd _plat planes, to enable quick recharging of the smaller chip capacitors. these bulk capacitors should have a low esr (equivalent series resistance) rating to ensure the quick response time necessary. they should also be connected to the power and ground planes through two vias to mi nimize inductance. suggested bulk capacitors: 100? 330 f (avx tps tantalum or sanyo oscon). 2.2 f (1) 0.003 f gnd 1.0 sd n av dd sv dd 2.2 f (1)
75 0926d?hirel?12/09 e2v semiconductors sas 2009 pc8610 [preliminary] 4.4 serdes block power suppl y decoupling recommendations the serdes block requires a clean, tightly regulated source of power (snv dd and xnv dd ) to ensure low jitter on transmit and reliable recovery of data in the receiver. an appropriate decoupling scheme is out- lined below. only surface mount technology (smt) capacitors sh ould be used to minimize inductance. connections from all capacitors to power and ground should be done with multiple vias to further reduce inductance. ? first, the board should have at least 10 10 nf smt ceramic chip capacitors as close as possible to the supply balls of the device. where the board ha s blind vias, these capacitors should be placed directly below the chip supply and ground connections. where the board does not have blind vias, these capacitors should be placed in a ring aroun d the device as close to the supply and ground connections as possible. ? second, there should be a 1 f ceramic chip capacito r on each side of the device. this should be done for all serdes supplies. ? third, between the device and any serdes voltage re gulator there should be a 10 f, low equivalent series resistance (esr) smt tantalum chip capacitor and a 100 f, low esr smt tantalum chip capacitor. this should be done for all serdes supplies. 4.5 connection recommendations to ensure reliable operation, it is highly recommended to connect unused inputs to an appropriate signal level. all unused active low in puts should be tied to v dd , bv dd , ov dd , gv dd , v dd _core, v dd _plat, xnv dd , and snv dd as required. all unused active high input s should be connected to gnd. all nc (no- connect) signals must remain unconnected. power and ground connections must be made to all external v dd , bv dd , ov dd , gv dd , v dd _core, v dd _plat, xnv dd , snv dd and gnd pins of the device. 4.6 pull-up and pull-dow n resistor requirements the pc8610 requires weak pull-up resistors (2?10 k is recommended) on open drain type pins includ- ing i 2 c pins and pic interrupt pins. correct operation of the jtag interface requires configuration of a group of system control pins as demonstrated in figure 4-6 on page 79 . care must be taken to ensure that these pins are maintained at a valid deasserted state under normal operating conditions as most have asynchronous b ehavior and spurious asserti on will give unpredictable results. refer to the pci 2.2 specificatio n for all pull-ups required for pci. the following pins must not be pulled down during power-on reset: lgpl0/ lgpl1, trig_out/ready, and msrcid[2]. the following are factory test pins and require strong pull up resistors (100 ?1 k ) to ov dd : lssd_mode, test_mode[0:3]. the following pins require weak pull up resistors (2?10 k ) to their specific power supplies: lcs [0:4], lcs [5]/dma_dreq2 , lcs [6]/dma_dack [2], lcs [7]/dma_ddone [2], irq_out, iic1_sda, iic1_scl, iic2_sda, iic2_scl, and ckstp_out. the following pins should be pulled to ground with a 100 resistor: sd1_imp_cal_tx, sd2_imp_cal_tx. the following pins should be pulled to ground with a 200 resistor: sd1_imp_cal_rx, sd2_imp_cal_rx. when the platform frequency is 400 mhz, cfg_platform_freq must be pulled down at reset. also, cfg_dram_type[0 or 1] must be valid at power -up even before hreset assertion.
76 0926d?hirel?12/09 pc8610 [preliminary] e2v semiconductors sas 2009 for other pin pull-up or pull-down recommendations of signals, please see section 2.1 ?pin assign- ments? on page 4 . 4.7 output buffer dc impedance the pc8610 drivers are characterized over process, voltage, and temperature. for all buses, the driver is a push-pull single-ended driver type (open drain for i 2 c). to measure z 0 for the single-ended drivers, an external resistor is connected from the chip pad to ov dd or gnd. then, the value of each resistor is varied until the pad voltage is ov dd /2 (see figure 4-4 ). the output impedance is the average of two components, the resistances of the pull-up and pull-down devices. when data is held high, sw1 is closed (sw2 is open) and r p is trimmed until the voltage at the pad equals ov dd /2. r p then becomes the resistance of the pull-up devices. r p and r n are designed to be close to each other in value. then, z 0 = (r p + r n )/2. figure 4-4. driver impedance measurement table 4-8 summarizes the signal impedance targets. the driver impedances are targeted at minimum v dd , nominal ov dd , t 0 = 125 c. note: nominal supply voltages. see table 3-2 on page 15 , t j = 125 c. table 4-8. impedance characteristics impedance local bus, duart, control, configuration, power management pci express ddr dram symbol unit r n 43 target 25 target 20 target z 0 r p 43 target 25 target 20 target z 0 ovdd ognd r p r n pad data sw1 sw2
77 0926d?hirel?12/09 e2v semiconductors sas 2009 pc8610 [preliminary] 4.8 configurati on pin muxing the pc8610 provides the user with power-on configuration options which can be set through the use of external pull-up or pull-down resistors of 4.7 k on certain output pins (see customer visible configuration pins). these pins are generally used as output only pins in normal operation. while hreset is asserted however, these pins are treat ed as inputs. the value presented on these pins while hreset is asserted, is latched when hreset deasserts, at which time the input receiver is disabled and the i/o circuit takes on its normal functi on. most of these sampled configuration pins are equipped with an on-chip gated resistor of approximately 20 k . this value should permit the 4.7-k resistor to pull the configuration pin to a valid logic low level. the pull-up resistor is enabled only during hreset (and for platform /sys tem clocks after hreset deassertion to ensure capture of the reset value). when the input receiver is disabled the pull-up is also, thus allowing functional operation of the pin as an output with minimal signal quality or delay disruption. the default value for all configuration bits treated this way has been encoded such that a high voltage level puts the device into the default state and external resistors are needed only when non-default settings are required by the user. careful board layout with stubless connections to these pull-down resistors coupled with the large value of the pull-down resistor should minimize the disrupti on of signal quality or speed for output pins thus configured. the platform pll ratio and e600 core pll ratio conf iguration pins are not equipped with these default pull-up devices. 4.9 jtag configuration signals correct operation of the jtag interface requires configuration of a group of system control pins as dem- onstrated in figure 4-6 on page 79 . care must be taken to ensure that these pins are maintained at a valid deasserted state under normal operating conditions as most have asynchronous behavior and spu- rious assertion will give unpredictable results. boundary-scan testing is enabled through the jtag interface signals. the trst signal is optional in the ieee 1149.1 specification, but is provided on all processors that implement the power architecture tech- nology. the device requires trst to be asserted during reset conditions to ensure the jtag boundary logic does not interfere with normal chip operation. while it is possible to force the tap controller to the reset state using only the tck and tms signals, more reliable power-on reset performance wil be obtained if the trst signal is asserted during power-on reset. because the jtag interface is also used for accessing the common on-chip processor (cop) function, simply tying trst to hreset is not practical. the cop function of these processors allows a remote computer system (typically a pc with dedicated hardware and debugging software) to access and control the internal operations of the processor. the cop port connects primarily through the jtag interface of the processor, with some additional status monitoring signals. the cop port requires the ability to independently assert hreset or trst in order to fully control the processor. if the target system has independent reset sources, such as voltage moni- tors, watchdog timers, power supply failures, or push-button switches, then the cop reset signals must be merged into these signals with logic. the arrangement shown in figure 4-5 on page 78 allows the cop port to independently assert hreset or trst , while ensuring that t he target can drive hreset as well. the cop interface has a standard header, shown in figure 4-5 on page 78 , for connection to the target system, and is based on the 0.025" square-post, 0.100" centered header assembly (often called a berg header). the connector typically has pin 14 removed as a connector key.
78 0926d?hirel?12/09 pc8610 [preliminary] e2v semiconductors sas 2009 the cop header adds many benefits such as breakpoi nts, watchpoints, register and memory examina- tion/modification, and other standard debugger featur es. an inexpensive option can be to leave the cop header unpopulated until needed. there is no standardized way to number the cop header shown in figure 4-6 on page 79 ; conse- quently, many different pin numbers have been observed from emulator vendors. some are numbered top-to-bottom then le ft-to-right, while others use left-to-right then top-to-bottom, while still others number the pins counter clockwise from pin 1 (as with an ic ). regardless of the numbering, the signal placement recommended in figure 4-6 is common to all known emulators. 4.9.1 termination of unused signals if the jtag interface and cop header will not be used, e2v recommends th e following connections: ?trst should be tied to hreset through a 0 k isolation resistor so that it is asserted when the system reset signal (hreset ) is asserted, ensuring that the jtag scan chain is initialized during the power-on reset flow. e2v recommends that the cop header be designed into the system as shown in figure 4-6 on page 79 . if this is not possible, the isolation resistor will allow future access to trst in case a jtag interface may need to be wired onto the system in future debug situations. ? tie tck to ov dd through a 10 k resistor. this will prevent tck from changing state and reading incorrect data into the device. ? no connection is required for tdi, tms, or tdo. figure 4-5. cop connector physical pinout 3 13 9 5 1 6 10 15 11 7 16 12 8 4 key no pin 1 2 cop_tdo cop_tdi nc nc cop_trst cop_vdd_sense cop_chkstp_in nc nc gnd cop_tck cop_tms cop_sreset cop_hreset cop_chkstp_out
79 0926d?hirel?12/09 e2v semiconductors sas 2009 pc8610 [preliminary] figure 4-6. jtag interface connection notes: 1. run/stop , normally found on pin 5 of the cop header, is not implemented. conne ct pin 5 of the cop header to ov dd with a 10-k pull-up resistor. 2. key location; pin 14 is not physically present on the cop header. hreset hreset from target board sources hreset 13 sreset sreset sreset nc nc 11 vdd_sense 6 5 1 15 2 k 10 k 10 k 10 k ov dd ov dd ov dd ov dd ckstp_in ckstp_in 8 tms tdo tdi tck tms tdo tdi tck 9 1 3 4 trst 7 16 2 10 12 (if any) cop header 14 2 ov dd ov dd 10 k ov dd trst 10 k ov dd 10 k 10 k ckstp_out ckstp_out 3 13 9 5 1 6 10 15 11 7 16 12 8 4 key no pin cop connector physical pin out 1 2 nc
80 0926d?hirel?12/09 pc8610 [preliminary] e2v semiconductors sas 2009 4.10 guidelines for high-s peed interface termination 4.10.1 serdes interface the high-speed serdes interface can be disabled through the por input cfg_io_ports[0:2] and through the devdisr register in software. if a serdes port is disabled through the por input the user can not enable it through the devdisr register in software. however, if a serdes port is enabled through the por input the user can disable it through the devdisr register in software. disabling a serdes port through software should be done on a temporary basis. power is always required for the serdes inter- face, even if the port is disabled through either mechanism. table 4-9 describes the possible enabled/disabled scenarios for a se rdes port. the termination recommendations must be followed for each port. notes: 1. partial termination when a serdes port is enabled thro ugh both por input and devdisr is determined by the serdes port mode. if port 1 is in x4 pci express mode, no termination is required because all pins are bei ng used. if port 1 is in x1/x2 pci express mode, termination is required on the unused pins. if port 2 is in x8 pci express mode, no termination is required because all pins are being used. if port 1 is in x1/x 2/x5 pci express mode, termination is required on the unused pins. 2. if a serdes port is enabled through the por input and th en disabled through devdisr, no hardware changes are required. termination of the serdes port should follow what is required when the port is enabled through both por input and devdisr. see note 1 for more information. if the high-speed serdes port requires complete or partial termination, the unused pins should be termi- nated as described in this section. the following pins must be left unconnected (floating): ?sd n _tx[7:0] ?sd n _tx [7:0] the following pins must be connected to gnd: ?sd n _rx[7:0] ?sd n _rx [7:0] ?sd n _ref_clk ? sd n _ref_clk for other directions on reserv ed or no-connects pins see section 2.1 ?pin assignments? on page 4 . table 4-9. serdes port enabled/disabled configurations disabled through por input enabled through por input enabled through devdisr serdes port is disabled (and cannot be enabled through devdisr) complete termination required (reference clock not required) serdes port is enabled partial termination may be required (1) (reference clock is required) disabled through devdisr serdes port is disabled (through por input) complete termination required (reference clock not required) serdes port is disabled after software disables port same termination requirements as when the port is enabled through por input (2) (reference clock is required)
81 0926d?hirel?12/09 e2v semiconductors sas 2009 pc8610 [preliminary] 4.11 guidelines for pci interface termination pci termination if pci is not used at all. option 1 if pci arbiter is enabled during por, ? all ad pins will be driven to the stable states afte r por. therefore, all ads pins can be floating. this includes pci_ad[31:0], pci_c/be [3:0] and pci_par signals. ? all pci control pins can be grouped together and tied to ov dd through a single 10 k resistor. ? it is optional to disable pci block through devdisr register after por reset. option 2 if pci arbiter is disabled during por, ? all ad pins will be in the input stat e. therefore, all ads pins need to be grouped toget her and tied to ov dd through a single (or multiple) 10 k resistor(s) ? all pci control pins can be grouped together and tied to ov dd through a single 10 k resistor ? it is optional to disable pci block through devdisr register after por reset. 4.12 thermal this section describes the thermal specifications of the pc8610. 4.13 thermal characteristics table 4-10 provides the package thermal characteristics for the pc8610. notes: 1. junction-to-ambient thermal resistance determined per jedec jesd51-3 and jesd51-6. thermal test board meets jedec specification for this package 2. junction-to-board thermal resistance determined per jedec jesd51-8. ther mal test board meets jedec specification for the specified package. 3. junction-to-case resistance is less than 0.1 c/w because the silicon die is the top of the packaging case. table 4-10. package thermal characteristics () characteristic symbol value unit notes junction-to-ambient thermal resistance, natural convection, single-layer (1s) board r ja 24 c/w (1) junction-to-ambient thermal resistance, natural convection, four-layer (2s2p) board r ja 18 c/w (1) junction-to-ambient thermal resistance, 200 ft/min airflow, single-layer (1s) board r jma 18 c/w (1) junction-to-ambient thermal resistance, 200 ft/min airflow, four-layer (2s2p) board r jma 15 c/w (1) junction-to-board thermal resistance r jb 10 c/w (2) junction-to-case th ermal resistance r jc < 0.1 c/w (3)
82 0926d?hirel?12/09 pc8610 [preliminary] e2v semiconductors sas 2009 4.14 thermal management information this section provides thermal management informa tion for the flip-chip, plastic ball-grid array (fc_pbga) package for air-cooled applications. proper thermal control design is primarily dependent on the system-level design: the heat sink, airflow, a nd thermal interface material. the pc8610 implements several features designed to assist with thermal management, including the temperature diode. the temperature diode allows an external device to moni tor the die temperature in order to detect excessive temperature conditions and alert the system; see section 4.14.5 ?temperature diode? on page 87 for more information. to reduce the die-junction temperature, heat sinks are required; due to the potential large mass of the heat sink, attachment through the printed-circuit board is suggested. in any implementation of a heat sink solution, the force on the die should not exceed ten pounds force (45 newtons). figure 4-7 shows a spring clip through the board. occasionally the spring clip is attached to soldered hooks or to a plastic backing structure. screw and spring arrangements are also frequently used. figure 4-7. fc-pbga package exploded cr oss-sectional view with several heat sink options suitable heat sinks are commercially available from the following vendors: aavid thermalloy 603-224-9988 80 commercial st. concord, nh 03301 internet: www.aavidthermalloy.com advanced thermal solutions 781-769-2800 89 access road #27. norwood, ma02062 internet: www.qats.com alpha novatech 408-749-7601 473 sapena ct. #12 santa clara, ca 95054 internet: www.alphanovatech.com calgreg thermal solutions 888-732-6100 60 alhambra road, suite 1 warwick, ri 02886 internet: www.calgreg.com thermal heat sink fc-pbga package heat sink clip interface material printed-circuit board
83 0926d?hirel?12/09 e2v semiconductors sas 2009 pc8610 [preliminary] international electronic research corporation (ierc) 818-842-7277 413 north moss st. burbank, ca 91502 internet: www.ctscorp.com millennium electronic s (mei) 408-436-8770 loroco sites 671 east brokaw road san jose, ca 95112 internet: www.mei-thermal.com tyco electronics 800-522-6752 chip coolers ? p.o. box 3668 harrisburg, pa 17105-3668 internet: www.chipcoolers.com wakefield engineering 603-635-5102 33 bridge st. pelham, nh 03076 internet: www.wakefield.com ultimately, the final selection of an appropriate heat sink depends on many factors, such as thermal per- formance at a given air velocity, spatial volume, mass, attachment method, assembly, and cost. 4.14.1 internal package conduction resistance for the exposed-die packaging technology described in table 4-10 on page 81 , the intrinsic conduction thermal resistance paths are as follows: ? the die junction-to-case thermal resistance ? the die junction-to-board thermal resistance figure 4-8 depicts the primary heat transfer path for a package with an attached heat sink mounted to a printed-circuit board. figure 4-8. c4 package with heat sink mounted to a printed-circuit board note the internal versus external package resistance external resistance external resistance internal resistance radiation convection heat sink thermal interface material die/package die junction package/leads printed-circuit board radiation convection
84 0926d?hirel?12/09 pc8610 [preliminary] e2v semiconductors sas 2009 the heat sink removes most of the heat from the device. heat generated on the active side of the chip is conducted through t he silicon, then th rough the heat sink attach materi al (or thermal interface material), and finally to the heat sink. the junction-to-case thermal resistance is low enough that the heat sink attach material and heat sink thermal resistance are the dominant terms. 4.14.2 thermal inte rface materials a thermal interface material is recommended at the pa ckage-to-heat sink interface to minimize the ther- mal contact resistance. figure 4-9 shows the thermal performance of three thin-sheet thermal-interface materials (silicone, graphite/o il, fluoroether oil), a bare joint, and a joint with thermal grease as a function of contact pressure. as shown, the performance of these thermal interface materials improves with increasing contact pressure. the use of thermal grease significantly reduces the interface thermal resis- tance. in contrast, the bare joint results in a thermal resistance approximately seven times greater than the thermal grease joint. often, heat sinks are attached to the package by means of a spring clip to holes in the printed-circuit board (see figure 4-7 on page 82 ). therefore, synthetic grease offers the best thermal performance, considering the low interface pressure, and is recommended. of course, the selection of any thermal interface material depends on many factors: thermal performance requirements, manufacturability, ser- vice temperature, dielectric properties, cost, and so on. figure 4-9. thermal performance of select thermal interface material 0 0.5 1 1.5 2 010 20304050607080 silicone sheet (0.006 in.) bare joint floroether oil sheet (0.007 in.) graphite/oil sheet (0.005 in.) synthetic grease contact pressure (psi) specific thermal resistance (k-in. 2 /w)
85 0926d?hirel?12/09 e2v semiconductors sas 2009 pc8610 [preliminary] the board designer can choose between several types of thermal interface. heat sink adhesive materi- als should be selected based on high conductivity and mechanical strength to meet equipment shock/vibration requirements. there are several commercially available thermal interfaces and adhesive materials provided by the following vendors: the bergquist company 800-347-4572 18930 west 78th st. chanhassen, mn 55317 internet: www.bergquistcompany.com chomerics, inc. 781-935-4850 77 dragon ct. woburn, ma 01801 internet: www.chomerics.com dow-corning corporation 800-248-2481 corporate center po box 994 midland, mi 48686-0994 internet: www.dowcorning.com shin-etsu microsi, inc. 888-642-7674 10028 s. 51st st. phoenix, az 85044 internet: www.microsi.com thermagon inc. 888-246-9050 4707 detroit ave. cleveland, oh 44102 internet: www.thermagon.com 4.14.3 heat sink selection example this section provides a heat sink selection example using one of the commercially available heat sinks. for preliminary heat sink sizing, the die-junc tion temperature can be expressed as follows: t j = t i + t r + (r jc + r int + r sa ) p d where: t j is the die-junction temperature t i is the inlet cabinet ambient temperature t r is the air temperature rise within the computer cabinet r jc is the junction-to-case thermal resistance r int is the adhesive or interface material thermal resistance r sa is the heat sink base-to-ambient thermal resistance p d is the power dissipated by the device
86 0926d?hirel?12/09 pc8610 [preliminary] e2v semiconductors sas 2009 during operation, the die-junction temperatures (t j ) should be maintained less than the value specified in table 3-2 on page 15 . the temperature of air cooling the component greatly depends on the ambient inlet air temperature and the air temperature rise withi n the electronic cabinet. an electronic cabinet inlet- air temperature (t i ) may range from 30 to 40 c. the air temperature rise within a cabinet (t r ) may be in the range of 5 to 10 c. the thermal resistance of the thermal interface material (r int ) is typically about 0.2 c/w. for example, assuming a t i of 30 c, a tr of 5 c, a package r jc = 0.1, and a typical power consumption (p d ) of 10 w, the following expression for t j is obtained: die-junction temperature: t j = 30 c + 5 c + (0.1 c/w + 0.2 c/w + sa ) 10 w for this example, a r sa value of 6.7 c/w or less is required to maintain the die junction temperature below the maximum value of table 3-2 on page 15 . though the die junction-to-ambient and the heat sink-to-ambient thermal resistances are a common fig- ure-of-merit used for comparing the thermal per formance of various microelectronic packaging technologies, one should exercise caution when only using this metric in determining thermal manage- ment because no single parameter can adequately descr ibe three-dimensional heat flow. the final die- junction operating temperature is not only a function of the component-level thermal resistance, but the system-level design and its operating conditions. in addition to the component's power consumption, a number of factors affect the final operating die-junction temperature: airflow, board population (local heat flux of adjacent components), heat sink efficiency, heat sink placement, next-level interconnect technol- ogy, system air temperature rise, altitude, and so on. due to the complexity and variety of system-level boundary conditions for today's microel ectronic equipment, the combined effects of the heat transfer mechanisms (radiation, convection, and conduction) may vary widely. for these reasons, we recom- mend using conjugate heat transfer models fo r the board as well as system-level designs. 4.14.4 recommended thermal model for system thermal modeling, the pc8610 thermal model is shown in figure 4-10 on page 87 . four cuboids are used to represent this device. the die is modeled as 8.5 9.7 mm at a thickness of 0.86 mm. see section 3.3 ?power characteristics? on page 19 for power dissipation details. the substrate is modeled as a single block 29 29 1.18 mm with orthotropic conductivity of 23.3 w/(m k) in the xy- plane and 0.95 w/(m k) in the z-direction. the die is centered on the substrate. the bump/underfill layer is modeled as a collapsed thermal resistance between the die and substrat e with a conductivity of 8.1 w/(m k) in the thickness dimension of 0.07 mm . the c5 solder layer is modeled as a cuboid with dimensions 29 29 0.4 mm with orthotropic thermal conductivity of 0.034 w/(m k) in the xy-plane and 12.1 w/(m k) in the z-direction. an lga solder layer would be modeled as a collapsed thermal resistance with thermal conductivity of 12.1 w/(m k) and an effective height of 0.1 mm. the thermal model uses median dimensions to reduce grid. pleas e refer to the case outline for actual dimensions. the thermal model uses approximate dimensions to reduce grid. the approximations used do not impact thermal performance. please refer to the case outline for exact dimensions.
87 0926d?hirel?12/09 e2v semiconductors sas 2009 pc8610 [preliminary] figure 4-10. pc8610 thermal model 4.14.5 temperature diode the pc8610 has a temperature diode on the microprocessor that can be used in conjunction with other system temperature monitoring devices (such as analog devices, adt7461 ? ). these devices use the negative temperature coefficient of a diode operated at a constant current to determine the temperature of the microprocessor and its environment. for proper operation, the monitoring device used should auto-calibrate the devic e by canceling ou t the vbe variation of each pc8610?s internal diode. the following are the specifications of the pc8610 on-board temperature diode: v f > 0.40v v f < 0.90v operating range 2?300 a diode leakage < 10 na at 125 c bump and underfill die substrate solder/air die substrate side view of model (not to scale) top view of model (not to scale) x y z conductivity value unit die (8.5 x 9.7 x 0.86mm) silicon temperature dependent bump and underfill (8.5 x 9.7 x 0.07 mm) collapsed resistance k z 8.1 w/(m . k) substrate (29 x 29 x 1.18 mm) k x 23.3 w/(m . k) k y 23.3 k z 0.95 solder and air (29 x 29 x 0.4 mm) k x 0.034 w/(m . k) k y 0.034 k z 12.1
88 0926d?hirel?12/09 pc8610 [preliminary] e2v semiconductors sas 2009 an approximate value of the ideality may be obtained by calibrating the device near the expected operat- ing temperature. ideality factor is defined as the deviation from the ideal diode equation: another useful equation is: where: i fw = forward current i s = saturation current v d = voltage at diode v f = voltage forward biased v h = diode voltage while i h is flowing v l = diode voltage while i l is flowing i h = larger diode bias current i l = smaller diode bias current q = charge of electron (1.6 10 ?19 c) n = ideality factor (normally 1.0) k = boltzman?s constant (1.38 10 ?23 joules/k) t = temperature (kelvins) the ratio of i h to i l is usually selected to be 10:1. the above simplifies to the following: v h ? v l = 1.986 10 ?4 nt solving for t, the equation becomes: i fw i s e qv f nkt ---------- - 1 ? = v h v l ? n kt q ------- in i h i l ----- = nt v h v l ? 1.986 10 4 ? ----------------------------------- =
89 0926d?hirel?12/09 e2v semiconductors sas 2009 pc8610 [preliminary] 5. package information this section details package parameters and dimensions. 5.1 package parameters for the pc8610 the package parameters are as provided in the following list. the package type is 29 mm 29 mm, 783 pins, leaded flip chip-pla stic ball grid array (fc-pbga). die size 8.5 mm 9.7 mm package outline 29 mm 29 mm interconnects 783 pitch 1 mm minimum module height 2.18 mm maximum module height 2.7 mm total capacitor count 23 caps; 100 nf each for leaded fc-cbga (package option: zf) solder balls 63% sn 37% pb ball diameter (typical) 0.50 mm for rohs lead-free fc-pbga (package option : vt) solder balls 96.5% sn 3.5% ag ball diameter (typical) 0.50 mm 5.2 mechanical dimensions of the pc8610 fc-pbga figure 5-1 on page 90 shows the mechanical dimensions and bo ttom surface nomenclature of the pc8610 fc-pbga.
90 0926d?hirel?12/09 pc8610 [preliminary] e2v semiconductors sas 2009 figure 5-1. pc8610 fc-pbga dimensions (zf package code) notes: 1. all dimensions are in millimeters. 2. dimensions and tolerances per asme y14.5m-1994. 3. maximum solder ball diameter measured parallel to datum a. 4. datum a, the seating plane, is defined by the spherical crowns of the solder balls. 5. capacitors may not be present on all devices. 6. caution must be taken not to short capacitors or expose metal capacitor pads on package top. 7. all dimensions symmetrical about centerlines unless otherwise specified. ag ae ac aa w u r n l j g e c a ah af ad ab y v t p m k h f d b bottom view topview a1 index 27 29 1 2 3 4 5 6 7 8 911 10 12 13 15 14 17 16 18 19 21 23 25 27 20 22 24 26 28 4 seating plane 0.2 a 783x 0.35 // a a b 5 6 0.25 abc m 0.1 a 3 783x 0.6 0.4 4x 6.8 max 0.5 27x 1 c 27x 1 27 0.5 4x 0.6 max 0.9 0.82 0.5 0.3 1.3 1.06 side view 2.70 2.18 0.25 a 4x capacitor zone 29 4x 11.35 max 4x 9.55 min 4x 0.15 9.762 9.562 8.559 8.359 7
91 0926d?hirel?12/09 e2v semiconductors sas 2009 pc8610 [preliminary] 6. ordering information ordering information for the parts fully covered by this specification document is provided in section 6.1 . 6.1 part numbers fully addressed by this document figure 6-1 provides the e2v part numbering nomenclature for the pc8610. note that the individual part numbers correspond to a maximum processor core frequency. for available frequencies, contact your local e2v sales office. in addition to the proces sor frequency, the part numbering scheme also includes an application modifier which may specify special application conditions. each part number also contains a revision code which refers to the die mask revision number. figure 6-1. ordering information notes: 1. for availability of the different versions, contact your local e2v sales office. 2. the letter x in the part number designates a "pro totype" product that has not been qualified by e2v. reliability of a pcx part-number is not guaranteed and such part-number shall not be used in flight hardware. product changes may still occur while shipping prototypes. 3. processor core frequencies supported by parts addressed by this specification only. not all parts described in this specification support all core frequencies. additionally, parts addressed by part num- ber specifications may support other maximum core frequencies. 7. definitions 7.1 life support applications these products are not designed for use in life s upport appliances, devices or systems where malfunc- tion of these products can reasonably be expected to result in personal injury. e2v customers using or selling these products fo r use in such applications do so at thei r own risk and agree to fully indemnify e2v for any damages resulting from such improper use or sale. xx xx x 8610 part identifier ddr speed (mhz) 8610 product code (1) pc(x) (2) package (1) revision level (1) zf = leaded sphere fc-pbga vt = rohs lead free fc-pbga x temperature range v: t c = -40 to t j = 110?c m: t c = -55 to t j = 125?c nnnn core processor frequency (mhz) 1333, 1066, 800 x j = 533 mhz g = 400 mhz revision b = 1.1 system version register value for rev b: 0x80a0_0011 - pc8610 (3) (1)
92 0926d?hirel?12/09 pc8610 [preliminary] e2v semiconductors sas 2009 8. document revision history table 8-1 provides a revision history for this hardware specification. table 8-1. document revision history rev. no date substantive change(s) 0926d 12/2009 updated figure 6-1 on page 91 : ordering information 0926c 11/2009 updated table 3-4 on page 19 and table 3-6 on page 20 : added maximum power consumption at t j = 125 c 0926b 12/2008 updated table 3-4 on page 19 : pc8610 power dissipation updated table 3-5 on page 20 : pc8610 individual supply maximum power dissipation added section 3.3.1 ?frequency derating? on page 20 added table 3-6 on page 20 : core frequency, platform frequency and power consumption derating updated table 4-1 on page 70 : processor core clocking specifications updated table 4-2 on page 70 : memory bus clocking specifications updated table 4-3 on page 71 : local bus clocking specifications updated table 4-4 on page 71 : platform/mpx bus clocking specifications updated table 4-7 on page 72 : sysclk and platform frequency options updated figure 6-1 on page 91 : ordering information 0926a 07/2008 initial revision
i 0926d?hirel?12/09 e2v semiconductors sas 2009 pc8610 [preliminary] table of contents features............... ................. .............. .............. .............. .............. ............. 1 overview.............. ................. .............. .............. .............. .............. ............. 1 screening ............ ................. .............. .............. .............. .............. ............. 1 1 block diagram ........... ................. ................ ................. ................ ............. 2 1.1 key features ......................................................................................................... 3 2 pin assignments and reset st ates ............... .............. .............. ............. 4 2.1 pin assignments ....................................................................................................4 3 electrical characteristics ... .............. .............. .............. .............. ........... 14 3.1 overall dc electrical characteristics .................................................................. 14 3.2 power sequencing .............................................................................................. 17 3.3 power characteristics ......................................................................................... 19 3.4 input clocks ......................................................................................................... 20 3.5 reset initialization ......... ................ ................. ................ ............. ............ .......... 23 3.6 ddr and ddr2 sdram ..................................................................................... 23 3.7 local bus ............................................................................................................. 30 3.8 display interface unit .......................................................................................... 35 3.9 i 2 c ....................................................................................................................... 38 3.10 duart ................................................................................................................ 40 3.11 fast/serial infrared interfaces (firi/siri) ........................................................... 41 3.12 synchronous serial interface (ssi) ..................................................................... 41 3.13 global timer module ........................................................................................... 46 3.14 gpio ................................................................................................................... 47 3.15 serial peripheral interface (spi) .......................................................................... 48 3.16 pci interface ....................................................................................................... 50 3.17 high-speed serial interfaces (hssi) ................................................................... 52 3.18 pci express ........................................................................................................ 61 3.19 jtag ................................................................................................................... 67
ii 0926d?hirel?12/09 pc8610 [preliminary] e2v semiconductors sas 2009 4 hardware design considerations .............. ................. .............. ........... 70 4.1 system clocking .................................................................................................. 70 4.2 power supply design and sequencing ............................................................... 73 4.3 decoupling recommendations ........................................................................... 74 4.4 serdes block power supply decoupling recommendations ............................. 75 4.5 connection recommendations ........................................................................... 75 4.6 pull-up and pull-down resistor requirements ................................................... 75 4.7 output buffer dc impedance .............................................................................. 76 4.8 configuration pin muxing .................................................................................... 77 4.9 jtag configuration signals ................................................................................ 77 4.10 guidelines for high-speed interface termination ............................................... 80 4.11 guidelines for pci interface termination ............................................................ 81 4.12 thermal ............................................................................................................... 81 4.13 thermal characteristics ...................................................................................... 81 4.14 thermal management information ...................................................................... 82 5 package information .............. ................. ................ ................. ............. 89 5.1 package parameters for the pc8610 .................................................................. 89 5.2 mechanical dimensions of the pc8610 fc-pbga ............................................. 89 6 ordering information ............ .............. .............. .............. .............. ......... 91 6.1 part numbers fully addressed by this document ............................................. 91 7 definitions ............. .............. .............. .............. .............. .............. ........... 91 7.1 life support applications ..................................................................................... 91 8 document revision history ... ................. ................ ................. ............. 92
0926d?hirel?12/09 e2v semiconductors sas 2009 whilst e2v has taken care to ensure the accuracy of the inform ation contained herein it accepts no responsibility for the conse quences of any use thereof and also reserves the right to change the specification of goods without notice. e2v accepts no liability beyond that set out i n its standard conditions of sale in respect of infringement of third party patents arising from the use of tubes or other devices in accordance with information contained herein. how to reach us home page: www.e2v.com sales offices: europe regional sales office e2v ltd 106 waterhouse lane chelmsford essex cm1 2qu england tel: +44 (0)1245 493493 fax: +44 (0)1245 492492 mailto: enquiries@e2v.com e2v sas 16 burospace f-91572 bivres cedex france tel: +33 (0) 16019 5500 fax: +33 (0) 16019 5529 mailto: enquiries-fr@e2v.com e2v gmbh industriestra?e 29 82194 gr?benzell germany tel: +49 (0) 8142 41057-0 fax: +49 (0) 8142 284547 mailto: enquiries-de@e2v.com americas e2v inc 520 white plains road suite 450 tarrytown, ny 10591 usa tel: +1 (914) 592 6050 or 1-800-342-5338, fax: +1 (914) 592-5148 mailto: enquiries-na@e2v.com asia pacific e2v ltd 11/f., onfem tower, 29 wyndham street, central, hong kong tel: +852 3679 364 8/9 fax: +852 3583 1084 mailto: enquiries-ap@e2v.com product contact: e2v avenue de rochepleine bp 123 - 38521 saint-egrve cedex france tel: +33 (0)4 76 58 30 00 hotline : mailto: std-hotline@e2v.com
iv 0926d?hirel?12/09 pc8610 [preliminary] e2v semiconductors sas 2009

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